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    Memory controllers, systems, and methods supporting multiple request modes
    21.
    发明公开
    Memory controllers, systems, and methods supporting multiple request modes 审中-公开

    公开(公告)号：US20230420010A1

    公开(公告)日：2023-12-28

    申请号：US18340803

    申请日：2023-06-23

    Applicant: Rambus Inc.

    Inventor： Richard E. Perego ,  Frederick A. Ware

    IPC: G11C7/10 ,  G06F13/16 ,  G11C5/06

    CPC classification number: G11C7/1072 ,  G06F13/1678 ,  G06F13/1684 ,  G06F13/1694 ,  G11C5/06 ,  G11C7/1045 ,  G11C7/1075

    Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

    Memory component with error-detect-correct code interface
    23.
    发明授权
    Memory component with error-detect-correct code interface 有权

    公开(公告)号：US11762737B2

    公开(公告)日：2023-09-19

    申请号：US17956516

    申请日：2022-09-29

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent S. Haukness ,  Lawrence Lai

    IPC: H03M13/27 ,  H04L27/34 ,  H04L1/00 ,  H03M13/25 ,  G06F11/10

    CPC classification number: G06F11/1076 ,  G06F11/1048

    Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

    Memory systems and methods for improved power management
    28.
    发明授权
    Memory systems and methods for improved power management 有权

    公开(公告)号：US11710520B2

    公开(公告)日：2023-07-25

    申请号：US17702475

    申请日：2022-03-23

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  James E. Harris

    IPC: G11C8/12 ,  G11C11/4093 ,  G11C5/04 ,  G11C5/06 ,  G11C7/22

    CPC classification number: G11C11/4093 ,  G11C5/04 ,  G11C5/063 ,  G11C7/22 ,  G11C8/12

    Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

    Protocol For Refresh Between A Memory Controller And A Memory Device
    29.
    发明公开
    Protocol For Refresh Between A Memory Controller And A Memory Device 审中-公开

    公开(公告)号：US20230223067A1

    公开(公告)日：2023-07-13

    申请号：US18078934

    申请日：2022-12-10

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent Haukness

    IPC: G11C11/406 ,  G06F13/16

    CPC classification number: G11C11/40611 ,  G06F13/1636 ,  G11C11/40615 ,  G11C11/406 ,  G11C11/40618 ,  Y02D10/00 ,  G11C2211/4067

    Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

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