公开(公告)号：US11416139B2

公开(公告)日：2022-08-16

申请号：US16492332

申请日：2018-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soyoung Kim ,  Daehyun Kim ,  Minsik Kim ,  Jongmoo Lee ,  Geon-Soo Kim ,  Jin-Wan An ,  Ji-Woo Lee ,  Hyun-Suk Choi

IPC: G06F3/04886 ,  G06F3/01 ,  G06F3/041 ,  G06F3/0484 ,  G06F3/14 ,  G06F3/16

Abstract: Provided are an electronic device and a screen display method of the electronic device. More specifically, provided are an electronic device for providing an extension function to a second area according to a characteristic of a characteristic area in first and second areas of an extended touch screen, and a screen display method of the electronic device. Some of the disclosed embodiments provide an electronic device for providing an extension function to a second area according to a characteristic of a characteristic area of an application screen in first and second areas divided by a trigger in an extended touch screen. In addition thereto, various other embodiments are also possible.

公开(公告)号：US11410724B2

公开(公告)日：2022-08-09

申请号：US16987618

申请日：2020-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo Lee ,  Daehyun Kim ,  Guyeon Wei

IPC: G11C16/08 ,  G11C16/24 ,  G11C7/10 ,  G11C16/30 ,  G11C16/04 ,  G11C16/26

Abstract: A semiconductor device is provided. The device includes a memory that stores data in a non-volatile and volatile manner and a memory controller configured to control the memory. The memory includes a word line pair including a first and second word line, a first bit line pair orthogonal to the first and the second word line and including a first bit line and a first complementary bit line, and a memory cell pair including first and second memory cells adjacent to the first memory cell in a word line direction. A left node of the first memory cell, and a right node of the first memory cell and a left node of the second memory cell, are all connected to the first word line, and a value of the data stored in the memory cell pair in the non-volatile manner is determined according to the selected first word line.

公开(公告)号：US10831405B2

公开(公告)日：2020-11-10

申请号：US15960644

申请日：2018-04-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chulseung Lee ,  Seonghoon Woo ,  Kyuwook Han ,  Daehyun Kim

IPC: G06F3/06 ,  G06F13/28

Abstract: A storage device includes a first memory device, a second memory device, and a controller. The first memory device and the second memory device share the same channel to communicate with the controller. Communication between the first memory device and the controller and communication between the second memory device and the controller are mutually exclusive. When the controller receives a read request directed to the second memory device while the controller processes a direct memory access (DMA) operation directed to the first memory device, the controller suspends the DMA operation and transmits a read command associated with the read request to the second memory device.

公开(公告)号：US12057713B2

公开(公告)日：2024-08-06

申请号：US17954825

申请日：2022-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomwoo Gu ,  Daehyun Kim ,  Jaeseok Park ,  Jaehyun Park ,  Sungku Yeo ,  Jeongman Lee

IPC: H02J50/12 ,  H02M1/12 ,  H02M7/48 ,  H03H7/40 ,  H03H11/30

CPC classification number: H02J50/12 ,  H02M1/126 ,  H02M7/4818 ,  H03H7/40 ,  H03H11/30

Abstract: A wireless power transmitting device includes: a transistor configured to output a signal corresponding to a set operating frequency, based on an input signal and a driving voltage; a matching circuit connected with the transistor; a transmission coil connected with the matching circuit; an LC resonance circuit connected in parallel between the transistor and the matching circuit and configured to transfer a signal corresponding to at least one harmonic frequency of the operating frequency; and an impedance sensing circuit connected with the LC resonance circuit and configured to sense a load impedance of the wireless power transmitting device based on the signal corresponding to the at least one harmonic frequency transferred through the LC resonance circuit. The matching circuit is configured to provide impedance matching with the sensed load impedance by adjusting an impedance of the matching circuit or an impedance of the transmission coil.

公开(公告)号：US20240178861A1

公开(公告)日：2024-05-30

申请号：US18339490

申请日：2023-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiho Kim ,  Seongmuk Kang ,  Daehyun Kim ,  Kijun Lee ,  Myungkyu Lee ,  Kyomin Sohn ,  Sunghye Cho

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/1111 ,  H03M13/611

Abstract: A memory controller to control a memory module including a plurality of data chips, a first parity chip and a second parity chip, includes a system error correction code (ECC) engine and a processor to control the system ECC engine. The system ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder selects one of a plurality of ECC decoding schemes based on decoding status flags and corrects a plurality of symbol errors in a read codeword set from the memory module by performing an ECC decoding on the read codeword set based on the selected decoding scheme and the parity check matrix. The decoding status flags are provided from the plurality of data chips and each of the decoding status flags indicates whether at least one error bit is detected in respective one of the plurality of data chips.

公开(公告)号：US11948851B2

公开(公告)日：2024-04-02

申请号：US17332471

申请日：2021-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunjae Kim ,  Eunsil Kang ,  Daehyun Kim ,  Sunkyoung Seo

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56

CPC classification number: H01L23/3192 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L21/561 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0557 ,  H01L2224/06519 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/29499 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161

Abstract: A semiconductor package includes a first semiconductor chip on a wiring structure, a plurality of internal terminals between the wiring structure and the first semiconductor chip; a high thermal conductivity layer is between the wiring structure and the first semiconductor chip; and an encapsulator on the high thermal conductivity layer and contacting the second semiconductor chip. Sidewalls of at least the wiring structure and the encapsulator are substantially coplanar.

公开(公告)号：US20230410925A1

公开(公告)日：2023-12-21

申请号：US18239548

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minho Choi ,  Jaeseong Lim ,  Kyungryun Kim ,  Daehyun Kim ,  Wonil Bae ,  Hohyun Shin ,  Sanghoon Jung ,  Hyongryol Hwang

IPC: G11C17/18 ,  G11C29/08 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C17/16 ,  G11C29/08

Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.

公开(公告)号：US11570516B2

公开(公告)日：2023-01-31

申请号：US16973938

申请日：2019-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjun Kim ,  Daehyun Kim ,  Hayeon Yoo ,  Sanghee Lee ,  Manchul Han

IPC: H04N21/45 ,  H04N21/466

Abstract: Disclosed is a display apparatus comprising: a display; a user input unit; and a processor configured to identify a user's viewing time based on a user's viewing history, create a list of content to be provided within the identified viewing time based on the viewing history and display the created content list on the display, and select at least one piece of content in the content list for viewing schedule based on a user input through the user input unit.

公开(公告)号：US11515712B2

公开(公告)日：2022-11-29

申请号：US16796134

申请日：2020-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungmin Lee ,  Daehyun Kim ,  Kiyoung Kim ,  Jaehyuck Shin ,  Youngho Ryu

IPC: H02J7/00

Abstract: A battery module including a plurality of battery sub packs and an electronic device including the battery module is provided. The battery module comprises a battery pack including a plurality of battery sub packs, a power delivery circuit connectable to the plurality of battery sub packs, a plurality of switches connected between the plurality of battery sub packs and the power delivery circuit, and at least one processor configured to control the plurality of switches to transmit power stored in a first battery sub pack to the power delivery circuit during a first time interval and transmit power stored in the power delivery circuit to a second battery sub pack during a second time interval. Other various embodiments are also provided herein.

公开(公告)号：US11462528B2

公开(公告)日：2022-10-04

申请号：US16459725

申请日：2019-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunmog Park ,  Daehyun Kim ,  Jinmin Kim ,  Hei Seung Kim ,  Hyunsik Park ,  Sangkil Lee

IPC: H01L27/115 ,  H01L25/18 ,  G11C14/00 ,  G11C16/04 ,  H01L25/00 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/48 ,  G11C13/00 ,  H01L27/11529

Abstract: Disclosed are fusion memory devices and methods of fabricating the same. The fusion memory device comprises a first memory device including a first substrate having active and inactive surfaces opposite to each other and a first memory cell circuit on the active surface of the first substrate, a non-memory device including a second substrate having active and inactive surfaces opposite to each other and a non-memory circuit on the active surface of the second substrate, the non-memory device being provided on the first memory device, and a second memory device on the inactive surface of the second substrate and including a second memory cell circuit different from the first memory cell circuit. The non-memory device lies between the first and second memory cell circuits and controls an electrical operation of each of the first and second memory cell circuits.