公开(公告)号：US20160351243A1

公开(公告)日：2016-12-01

申请号：US15160076

申请日：2016-05-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Shuhei NAGATSUKA ,  Tatsuya ONUKI ,  Yutaka SHIONOIRI ,  Naoaki TSUTSUI ,  Shunpei YAMAZAKI

IPC: G11C11/40 ,  H01L27/12 ,  G11C5/06 ,  G11C7/12 ,  G11C8/08 ,  H01L23/528 ,  H01L27/105 ,  G11C11/24

CPC classification number: H01L27/1207 ,  G11C5/063 ,  G11C11/401 ,  G11C11/4097 ,  G11C2029/0403 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255

Abstract: A memory device in which the number of films is reduced. The memory device includes a circuit and a wiring. The circuit includes a first memory cell and a second memory cell. The first memory cell includes a first transistor, a second transistor, and a first capacitor. The second memory cell includes a third transistor, a fourth transistor, and a second capacitor. The second memory cell is stacked over the first memory cell. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and the first capacitor. One of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor and the second capacitor. A gate of the first transistor and a gate of the third transistor are electrically connected to the wiring.

Abstract translation: 一种其中薄膜数量减少的存储器件。 存储器件包括电路和布线。 电路包括第一存储单元和第二存储单元。 第一存储单元包括第一晶体管，第二晶体管和第一电容器。 第二存储单元包括第三晶体管，第四晶体管和第二电容器。 第二存储单元堆叠在第一存储单元上。 第一晶体管的源极和漏极之一电连接到第二晶体管的栅极和第一电容器。 第三晶体管的源极和漏极之一电连接到第四晶体管和第二电容器的栅极。 第一晶体管的栅极和第三晶体管的栅极电连接到布线。

公开(公告)号：US20150349131A1

公开(公告)日：2015-12-03

申请号：US14723630

申请日：2015-05-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Yoshiyuki KOBAYASHI ,  Yutaka SHIONOIRI ,  Yuto YAKUBO ,  Shuhei NAGATSUKA ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/04 ,  H01L29/24

CPC classification number: H01L29/7869 ,  G05F3/262 ,  H01L27/085 ,  H01L27/0886 ,  H01L27/1211 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/7782 ,  H01L29/785 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device which occupies a small area is provided. A semiconductor device includes a resistor. The resistor includes a transistor. The increase rate of a drain current of the transistor with a 0.1 V change in drain voltage is preferably higher than or equal to 1% when the drain voltage is higher than a difference between a gate voltage and a threshold voltage of the transistor. The semiconductor device has a function of generating a voltage based on the resistance of the resistor.

Abstract translation: 提供占据小面积的半导体器件。 半导体器件包括电阻器。 电阻器包括晶体管。 当漏极电压高于晶体管的栅极电压和阈值电压之间的差时，漏极电压的0.1V变化的晶体管的漏极电流的增加率优选地高于或等于1％。 半导体器件具有基于电阻器的电阻产生电压的功能。

公开(公告)号：US20150325708A1

公开(公告)日：2015-11-12

申请号：US14704101

申请日：2015-05-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuto YAKUBO ,  Suguru HONDO ,  Akihisa SHIMOMURA ,  Shunpei YAMAZAKI ,  Shuhei NAGATSUKA

IPC: H01L29/786 ,  H01L29/36 ,  H01L29/423 ,  H01L27/06 ,  H01L27/092 ,  H01L29/04 ,  H01L29/10

CPC classification number: H01L27/0688 ,  H01L21/8258 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/423 ,  H01L29/4238 ,  H01L29/7869 ,  H01L29/78696

Abstract: A transistor capable of being driven at high operating frequency is provided. The transistor includes first to third oxide semiconductor layers, a gate insulating layer, a gate electrode layer, and a portion in which the first to third oxide semiconductor layers are sequentially stacked. Channel length is less than 100 nm, and cutoff frequency at a source-drain voltage of higher than or equal to 1 V and lower than or equal to 2 V is higher than 1 GHz. The gate insulating layer is in contact with a top surface of the third oxide semiconductor layer. The gate electrode layer partly overlaps with the portion with the gate insulating layer positioned therebetween. The second oxide semiconductor layer includes a plurality of c-axis aligned crystal parts and a region in which the concentration of hydrogen measured by secondary ion mass spectrometry is lower than 2×1020 atoms/cm3.

Abstract translation: 提供能够以高工作频率驱动的晶体管。 晶体管包括第一至第三氧化物半导体层，栅极绝缘层，栅极电极层以及其中第一至第三氧化物半导体层顺序堆叠的部分。 通道长度小于100nm，源极 - 漏极电压高于或等于1V且低于或等于2V的截止频率高于1GHz。 栅极绝缘层与第三氧化物半导体层的顶表面接触。 栅极电极层与位于其间的栅极绝缘层的部分重叠。 第二氧化物半导体层包括多个c轴取向晶体部分和通过二次离子质谱法测量的氢浓度低于2×1020原子/ cm3的区域。

公开(公告)号：US20150255139A1

公开(公告)日：2015-09-10

申请号：US14637542

申请日：2015-03-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Tamae MORIWAKA ,  Yuta ENDO

IPC: G11C11/24 ,  H01L27/115 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L27/115 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  G11C11/4085 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/1156 ,  H01L29/24 ,  H01L29/7869

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≧2, the jth sub memory cell is arranged over the j−1th sub memory cell.

Abstract translation: 提供适于小型化的半导体器件。 提供高度可靠的半导体器件。 提供具有改善的操作速度的半导体器件。 [解决方案]一种半导体器件，包括第一至第C（c是2个或更多个的自然数）子存储单元的存储单元，其中：第j子存储单元包括第一晶体管，第二晶体管和电容器; 包括在第一晶体管中的第一半导体层和包括在第二晶体管中的第二半导体层包括氧化物半导体; 电容器的端子之一电连接到包括在第二晶体管中的栅电极; 包括在第二晶体管中的栅电极电连接到包括在第一晶体管中的源电极和漏极之一; 并且当j≥2时，第j个子存储单元布置在第j-1个子存储单元上。

公开(公告)号：US20150123183A1

公开(公告)日：2015-05-07

申请号：US14595692

申请日：2015-01-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi KATO ,  Shuhei NAGATSUKA

IPC: H01L27/11

CPC classification number: H01L27/1108 ,  G11C16/0408 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/60

Abstract: A semiconductor device with a novel structure is provided in which stored data can be held even when power is not supplied and the number of writing is not limited. The semiconductor includes a second transistor and a capacitor over a first transistor. The capacitor includes a source or drain electrode and a gate insulating layer of the second transistor and a capacitor electrode over an insulating layer which covers the second transistor. The gate electrode of the second transistor and the capacitor electrode overlap at least partly with each other with the insulating layer interposed therebetween. By forming the gate electrode of the second transistor and the capacitor electrode using different layers, an integration degree of the semiconductor device can be improved.

Abstract translation: 提供具有新颖结构的半导体器件，其中即使在不提供电力并且写入次数不受限制的情况下，也可以保持存储的数据。 半导体在第一晶体管上包括第二晶体管和电容器。 电容器包括源极或漏极以及第二晶体管的栅极绝缘层，以及覆盖第二晶体管的绝缘层上的电容器电极。 第二晶体管的栅电极和电容器电极至少部分地彼此重叠，绝缘层位于它们之间。 通过使用不同层来形成第二晶体管的栅电极和电容电极，可以提高半导体器件的集成度。

公开(公告)号：US20130181216A1

公开(公告)日：2013-07-18

申请号：US13795244

申请日：2013-03-12

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Toshihiko SAITO ,  Takanori MATSUZAKI ,  Shuhei NAGATSUKA ,  Hiroki INOUE

IPC: H01L29/78

CPC classification number: H01L29/78 ,  G11C11/403 ,  G11C11/406 ,  G11C16/0416 ,  G11C2211/4065 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225

Abstract: A semiconductor device includes a plurality of memory cells including a first transistor and a second transistor, a reading circuit including an amplifier circuit and a switch element, and a refresh control circuit. A first channel formation region and a second channel formation region contain different materials as their respective main components. A first gate electrode is electrically connected to one of a second source electrode and a second drain electrode. The other of the second source electrode and the second drain electrode is electrically connected to one of input terminals of the amplifier circuit. An output terminal of the amplifier circuit is connected to the other of the second source electrode and the second drain electrode through the switch element. The refresh control circuit is configured to control whether the switch element is turned on or off.

Abstract translation: 一种半导体器件包括多个包括第一晶体管和第二晶体管的存储单元，包括放大器电路和开关元件的读取电路以及刷新控制电路。 第一通道形成区域和第二通道形成区域包含不同的材料作为它们各自的主要成分。 第一栅电极电连接到第二源电极和第二漏极之一。 第二源极和第二漏极中的另一个电连接到放大器电路的一个输入端。 放大器电路的输出端子通过开关元件连接到第二源电极和第二漏电极中的另一个。 刷新控制电路被配置为控制开关元件是打开还是关闭。

公开(公告)号：US20240194252A1

公开(公告)日：2024-06-13

申请号：US18584118

申请日：2024-02-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Seiya SAITO ,  Yuto YAKUBO ,  Tatsuya ONUKI ,  Shuhei NAGATSUKA

IPC: G11C11/4097 ,  G11C11/4091 ,  H01L29/786 ,  H10B12/00

CPC classification number: G11C11/4097 ,  G11C11/4091 ,  H01L29/7869 ,  H10B12/30 ,  H10B12/50

Abstract: A novel semiconductor device is provided. The semiconductor device includes a driver circuit including a plurality of transistors using a silicon substrate for channels, and a first transistor layer and a second transistor layer including a plurality of transistors using a metal oxide for channels. The first transistor layer and the second transistor layer are provided over the silicon substrate layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The first transistor is electrically connected to a first local bit line. The second transistor layer includes a second transistor whose gate is electrically connected to the first local bit line and a first correction circuit electrically connected to the second transistor. The first correction circuit is electrically connected to a first global bit line. The first correction circuit has a function of holding a voltage corresponding to a threshold voltage of the second transistor in the gate of the second transistor.

公开(公告)号：US20230283276A1

公开(公告)日：2023-09-07

申请号：US18016888

申请日：2021-07-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takayuki IKEDA ,  Shuhei NAGATSUKA

IPC: H03K17/687 ,  G06F7/544 ,  H01L29/786

CPC classification number: H03K17/687 ,  G06F7/5443 ,  H01L29/7869 ,  G06F2207/4824 ,  G06G7/16

Abstract: A semiconductor device with high arithmetic performance is provided. The semiconductor device employs the translinear principle, and the semiconductor device includes first to tenth transistors each including a metal oxide in a channel formation region and a first capacitor. A first terminal of the first transistor is electrically connected to a first terminal of the second transistor, a first terminal of the third transistor is electrically connected to a second terminal of the second transistor and a gate of the second transistor through the first capacitor. The second terminal of the second transistor is electrically connected to first terminals of the fourth and the seventh transistors and gates of the fifth and the eighth transistors. A gate of the seventh transistor is electrically connected to first terminals of the fifth and the sixth transistors, and a gate of the tenth transistor is electrically connected to first terminals of the eighth and the ninth transistors.

公开(公告)号：US20220352384A1

公开(公告)日：2022-11-03

申请号：US17760836

申请日：2020-09-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi OOTA ,  Yoshinori ANDO ,  Shuhei NAGATSUKA ,  Tatsuki KOSHIDA ,  Satoru OHSHITA ,  Ryota HODO ,  Kazuki TSUDA ,  Akio SUZUKI

IPC: H01L29/786 ,  H01L27/108 ,  H01L29/66

Abstract: A semiconductor device that is suitable for high integration is provided. A first layer provided with a first transistor including an oxide semiconductor, over a substrate; a second layer over the first layer; a third layer provided with a second transistor including an oxide semiconductor, over the second layer; a fourth layer between the first layer and the second layer; and a fifth layer between the second layer and the third layer are included. The total internal stress of the first layer and the total internal stress of the third layer act in a first direction, the total internal stress of the second layer acts in the direction opposite to the first direction, and the fourth layer and the fifth layer each include a film having a barrier property.

公开(公告)号：US20220310616A1

公开(公告)日：2022-09-29

申请号：US17635740

申请日：2020-08-11

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shuhei NAGATSUKA ,  Tatsuya ONUKI ,  Shunpei YAMAZAKI

IPC: H01L27/108 ,  G11C5/10 ,  H01L23/522 ,  H01L23/528

Abstract: A memory device occupying a small area is provided. In a memory cell including a reading transistor, a writing transistor, and a capacitor, the writing transistor is provided above the reading transistor. Alternatively, the reading transistor is provided above the writing transistor. An oxide semiconductor is used for a semiconductor layer where a channel of the writing transistor is formed. An oxide semiconductor is used for a semiconductor layer where a channel of the reading transistor is formed. Memory cells are arranged in a matrix.