公开(公告)号：US20180090616A1

公开(公告)日：2018-03-29

申请号：US15697896

申请日：2017-09-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takashi NAKAGAWA ,  Yoshiyuki KUROKAWA ,  Munehiro KOZUMA

IPC: H01L29/786 ,  H01L29/16 ,  H01L29/24 ,  H01L27/12 ,  H03K19/00 ,  H03K19/177

CPC classification number: H01L29/7869 ,  H01L27/1207 ,  H01L27/28 ,  H01L29/16 ,  H01L29/24 ,  H03K19/0013 ,  H03K19/17708 ,  H03K19/17744

Abstract: A novel semiconductor device is provided. The semiconductor device includes a programmable logic device including a programmable logic element, a control circuit, and a detection circuit. The programmable logic device includes a plurality of contexts. The control circuit is configured to control selection of the contexts. The detection circuit is configured to output a signal corresponding to the amount of radiation. The control circuit is configured to switch between a first mode and a second mode in accordance with the signal corresponding to the amount of radiation. The first mode is a mode in which the programmable logic device performs processing by a multi-context method, and the second mode is a mode in which the programmable logic device performs processing using a majority signal of signals output from the logic element multiplexed by the plurality of contexts.

公开(公告)号：US20170053699A1

公开(公告)日：2017-02-23

申请号：US15232106

申请日：2016-08-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeshi AOKI ,  Munehiro KOZUMA ,  Yoshiyuki KUROKAWA

IPC: G11C14/00 ,  H03K19/177 ,  H01L27/06 ,  H01L27/12

CPC classification number: G11C14/0054 ,  G11C11/24 ,  G11C14/00 ,  H01L27/0688 ,  H01L27/1225 ,  H03K3/356008 ,  H03K19/1776 ,  H03K19/17764

Abstract: A semiconductor device that has a long data retention time during stop of supply of power supply voltage by reducing leakage current due to miniaturization of a semiconductor element. In a structure where charge corresponding to data is held with the use of low off-state current of a transistor containing an oxide semiconductor in its channel formation region, a transistor for reading data and a transistor for storing charge are separately provided, thereby decreasing leakage current flowing through a gate insulating film.

Abstract translation: 一种半导体器件，其通过减少由于半导体元件的小型化引起的漏电流而在停止供给电源电压期间具有长的数据保持时间。 在使用在其沟道形成区域中含有氧化物半导体的晶体管的低截止电流来保持对应于数据的电荷的结构中，分别提供用于读取数据的晶体管和用于存储电荷的晶体管，从而减少泄漏 电流流过栅极绝缘膜。

公开(公告)号：US20160380630A1

公开(公告)日：2016-12-29

申请号：US15191763

申请日：2016-06-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro KOZUMA ,  Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Takeshi AOKI

IPC: H03K19/00 ,  H03K19/173 ,  H03K19/177 ,  H01L27/12 ,  H01L29/786

CPC classification number: H03K19/0013 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/7869 ,  H03K19/09441 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17748 ,  H03K19/1776

Abstract: A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor.

公开(公告)号：US20160240239A1

公开(公告)日：2016-08-18

申请号：US15138318

申请日：2016-04-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takayuki IKEDA ,  Yoshiyuki KUROKAWA ,  Munehiro KOZUMA

IPC: G11C11/24 ,  G11C7/16 ,  H01L29/786 ,  H01L27/105 ,  G11C27/02 ,  H01L27/12 ,  H01L23/528 ,  H01L29/66 ,  H01L21/02 ,  G11C11/40 ,  G11C27/00

CPC classification number: G11C11/24 ,  G11C7/16 ,  G11C11/40 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C16/0441 ,  G11C16/10 ,  G11C27/005 ,  G11C27/02 ,  G11C27/024 ,  H01L21/02565 ,  H01L21/0262 ,  H01L23/528 ,  H01L27/1052 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

Abstract: A semiconductor device capable of generating a signal (e.g., a potential signal or a current signal) suitable for usage environment or a purpose. The semiconductor device includes a first memory circuit, a first circuit, and a second memory circuit. The first circuit converts a digital signal input from the first memory circuit into an analog signal. The first memory circuit includes an input node, an output node, a transistor, and a capacitor. The capacitor is electrically connected to the output node. The transistor can control a conduction state between the input node and the output node. An analog signal is input to the input node from the first circuit. The transistor includes an oxide semiconductor layer where a channel formation region is formed.

公开(公告)号：US20160021319A1

公开(公告)日：2016-01-21

申请号：US14799006

申请日：2015-07-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuki OKAMOTO ,  Munehiro KOZUMA ,  Yoshiyuki KUROKAWA

IPC: H04N5/363 ,  H01L27/146 ,  H04N5/3745

CPC classification number: H04N5/363 ,  H01L27/14612 ,  H01L27/14627 ,  H01L27/14643 ,  H01L27/14665 ,  H04N5/3575 ,  H04N5/378

Abstract: A novel semiconductor device, a semiconductor device where influence of noise is lessened, or a semiconductor device with high reliability is provided. A first circuit has a function of generating an optical data signal in accordance with the amount of irradiation light and a function of generating a reset signal corresponding to a reset state of the first circuit. A second circuit has a function of controlling output of the optical data signal and the reset signal from the first circuit to a fourth circuit. A third circuit has a function of controlling generation of the reset signal to be output from the first circuit to the fourth circuit. The fourth circuit has a function of calculating the difference between the optical data signal input from the first circuit and the reset signal input from the first circuit after input of the optical data signal.

Abstract translation: 提供了一种新颖的半导体器件，其中降低噪声影响的半导体器件或者具有高可靠性的半导体器件。 第一电路具有根据照射光的量产生光学数据信号的功能，以及产生与第一电路的复位状态对应的复位信号的功能。 第二电路具有控制光数据信号的输出和从第一电路到第四电路的复位信号的功能。 第三电路具有控制从第一电路输出到第四电路的复位信号的产生的功能。 第四电路具有计算在输入光数据信号之后从第一电路输入的光数据信号与从第一电路输入的复位信号之间的差的功能。

公开(公告)号：US20150256177A1

公开(公告)日：2015-09-10

申请号：US14635087

申请日：2015-03-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro KOZUMA ,  Takayuki IKEDA ,  Yoshiyuki KUROKAWA ,  Takeshi AOKI ,  Takashi NAKAGAWA

IPC: H03K19/00 ,  G06F1/16 ,  H03K19/177 ,  H01L29/786 ,  H01L27/12

CPC classification number: H03K19/0008 ,  G06F1/16 ,  H01L27/1207 ,  H01L29/42384 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696 ,  H03K19/1776

Abstract: A semiconductor device in which operation delay due to stop and restart of the supply of a power supply potential is suppressed is provided. Potentials corresponding to data held in first and second nodes while the supply of a power supply potential is continued are backed up in third and fourth nodes while the supply of the power supply potential is stopped. After the supply of the power supply potential is restarted, data are restored to the first and second nodes by utilizing a change in channel resistance of a transistor whose gate is electrically connected to the third or fourth node. Note that shoot-through current is suppressed at the time of data restoration by electrically disconnecting the power supply potential and the first or second node from each other.

Abstract translation: 提供了一种半导体装置，其中抑制了由于电源电位供应的停止和重启而导致的操作延迟。 在电源电位的供给停止的同时，在供给电源电位的同时保持在第一节点和第二节点上的数据对应的电位被备份在第三节点和第四节点中。 在重新开始供电电位之后，通过利用栅极电连接到第三或第四节点的晶体管的沟道电阻的变化，将数据恢复到第一和第二节点。 注意，通过将电源电位和第一或第二节点彼此电断开来，在数据恢复时抑制直通电流。

公开(公告)号：US20250054523A1

公开(公告)日：2025-02-13

申请号：US18932891

申请日：2024-10-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeshi AOKI ,  Yoshiyuki KUROKAWA ,  Munehiro KOZUMA ,  Takuro KANEMURA ,  Tatsunori INOUE

IPC: G11C5/10 ,  G11C11/22 ,  H01L29/66 ,  H01L29/78 ,  H10B53/30

Abstract: A semiconductor device with a small circuit area and low power consumption is provided. The semiconductor device includes first to fourth cells, a current mirror circuit, and first to fourth wirings, and the first to fourth cells each include a first transistor, a second transistor, and a capacitor. In each of the first to fourth cells, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. The first wiring is electrically connected to first terminals of the second transistors in the first cell and the second cell, the second wiring is electrically connected to first terminals of the second transistors in the third cell and the fourth cell, the third wiring is electrically connected to second terminals of the capacitors in the first cell and the third cell, and the fourth wiring is electrically connected to second terminals of the capacitors in the second cell and the fourth cell. The current mirror circuit is electrically connected to the first wiring and the second wiring.

公开(公告)号：US20240331641A1

公开(公告)日：2024-10-03

申请号：US18293869

申请日：2022-07-28

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Munehiro KOZUMA ,  Tatsuya ONUKI ,  Hidetomo KOBAYASHI

IPC: G09G3/3266 ,  G06F3/042 ,  G06V40/13 ,  G09G3/3233

CPC classification number: G09G3/3266 ,  G06F3/042 ,  G06V40/1318 ,  G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0842 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G09G2354/00 ,  G09G2360/14

Abstract: To provide a display apparatus with a novel structure. A display portion including a first subpixel, a second subpixel, a first gate line supplied with a first selection signal to scan the first subpixel, and a second gate line supplied with a second selection signal to scan the second subpixel; and a driver control circuit including a gate line driver circuit, a switching portion that allots the first selection signal or the second selection signal output from the gate line driver circuit to the first gate line or the second gate line to be output, and a timing control circuit that controls the switching portion are included. The timing control circuit allows the gate line driver circuit to output the first selection signal of a first frame frequency and the second selection signal having a selection period longer than the first selection signal in a first operation mode, and to output the first selection signal and the second selection signal with a second frame frequency lower than the first frame frequency in a second operation mode.

公开(公告)号：US20240321205A1

公开(公告)日：2024-09-26

申请号：US18569779

申请日：2022-06-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Tatsuya ONUKI ,  Hidetomo KOBAYASHI ,  Munehiro KOZUMA ,  Takanori MATSUZAKI ,  Susumu KAWASHIMA ,  Yutaka OKAZAKI

IPC: G09G3/3233 ,  H01L27/088 ,  H01L27/12

CPC classification number: G09G3/3233 ,  H01L27/088 ,  H01L27/1225 ,  G09G2300/0426 ,  G09G2300/0852 ,  G09G2330/021

Abstract: The invention of the application is the invention regarding a semiconductor device and a method for driving the semiconductor device. The semiconductor device includes first and second transistors, first to fifth switches, first to third capacitors, and a display element. The first transistor (M2) comprises a back gate, a gate of the first transistor is electrically connected to the first switch (M1), the second switch (M3) and the first capacitor (C1) are positioned between the gate of the first transistor and a source of the first transistor, the back gate of the first transistor is electrically connected to the third switch (M4), the second capacitor (C2) is positioned between the back gate of the first transistor and the source of the first transistor, the source of the first transistor is electrically connected to the fourth switch (M6) and a drain of the second transistor (M5), a gate of the second transistor is electrically connected to the fifth switch (M7), the third capacitor (C3) is positioned between the gate of the second transistor and a source of the second transistor, and the source of the second transistor is electrically connected to the display element (61).

公开(公告)号：US20230176818A1

公开(公告)日：2023-06-08

申请号：US17922064

申请日：2021-05-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Minato ITO ,  Munehiro KOZUMA ,  Yuki OKAMOTO

IPC: G06F7/544 ,  G06N3/063 ,  H01L29/786 ,  H01L27/06

CPC classification number: G06F7/5443 ,  G06N3/063 ,  H01L29/7869 ,  H01L27/0688

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a storage circuit, an arithmetic circuit, and a driver circuit. The arithmetic circuit includes a switching circuit and a product-sum operation circuit. The storage circuit includes a first storage region and a second storage region. The first storage region has a function of retaining first storage data. The second storage region has a function of retaining second storage data. The switching circuit has a function of outputting the first storage data or the second storage data to the product-sum operation circuit. The driver circuit has a function of outputting first input data or second input data to the product-sum operation circuit. The product-sum operation circuit has a function of retaining first output data obtained by arithmetic processing performed on the first input data and the first storage data selected by the switching circuit. The arithmetic circuit has a function of adding, to the first output data, second output data obtained by arithmetic processing performed on the second input data and the second storage data selected by the switching circuit.