公开(公告)号：US06876066B2

公开(公告)日：2005-04-05

申请号：US09944246

申请日：2001-08-30

Applicant: Setho Sing Fee ,  Lim Thiam Chye ,  Eric Tan Swee Seng

Inventor： Setho Sing Fee ,  Lim Thiam Chye ,  Eric Tan Swee Seng

IPC: H01L21/56 ,  H01L21/68 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L21/568 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49558 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/85001 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Microelectronic devices in accordance with aspects of the invention may include a die, a plurality of lead fingers and an encapsulant which may bond the lead fingers and the die. In one method of the invention, a lead frame and a die are releasably attached to a support, an encapsulant is applied, and the support can be removed to expose back contacts of the lead fingers and a back surface of the die. One microelectronic device assembly of the invention includes a die having an exposed back die surface; a plurality of electrical leads, each of which includes front and back electrical contacts; bonding wires electrically coupling the die to the electrical leads; and an encapsulant bonded to the die and the electrical leads. The rear electrical contacts of the electrical leads may be exposed adjacent a back surface of the encapsulant in a staggered array.

公开(公告)号：US06773960B2

公开(公告)日：2004-08-10

申请号：US10435423

申请日：2003-05-08

Applicant: Setho Sing Fee ,  Tay Wuu Yean ,  Lim Thiam Chye

Inventor： Setho Sing Fee ,  Tay Wuu Yean ,  Lim Thiam Chye

IPC: H01L2148

CPC classification number: H01L24/97 ,  H01L21/4803 ,  H01L23/13 ,  H01L23/49811 ,  H01L24/45 ,  H01L24/48 ,  H01L24/50 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/181 ,  H05K3/0044 ,  H05K2203/0228 ,  H05K2203/1476 ,  Y10T408/03 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00

Abstract: An interposer includes a substantially planar substrate with a slot formed therethrough. The slot includes a laterally recessed area formed in only a portion of a periphery thereof, which is positioned so as to expose at least a portion of an active surface of the semiconductor die located between a bond pad and an outer periphery of the semiconductor die. The laterally recessed area facilitates access to the bond pad by apparatus for forming, positioning, or securing intermediate conductive elements. The slot may be formed by forming a first, thin elongated slot through the interposer substrate, then widening a portion thereof. Alternatively, a first, small circular hole may be formed through the interposer substrate, then an elongated slot having a width that exceeds the diameter of the small circular hole may be formed through the substrate at a location which is continuous with the small circular hole.

Abstract translation: 插入器包括具有穿过其形成的狭槽的基本平坦的基板。 狭槽包括只形成在其周边的一部分中的横向凹入区域，其被定位成暴露位于半导体管芯的接合焊盘和外周之间的半导体管芯的有源表面的至少一部分。 横向凹陷区域便于通过用于形成，定位或固定中间导电元件的设备进入接合焊盘。 槽可以通过形成通过插入器基板的第一细长狭缝，然后加宽其一部分而形成。 或者，可以通过插入器基板形成第一小圆形孔，然后可以在与小圆孔连续的位置处形成具有超过小圆孔直径的宽度的细长槽。

公开(公告)号：US06537857B2

公开(公告)日：2003-03-25

申请号：US09849671

申请日：2001-05-07

Applicant: Weddie Aquien ,  John Briar ,  Setho Sing Fee

Inventor： Weddie Aquien ,  John Briar ,  Setho Sing Fee

IPC: H01L2144

CPC classification number: H01L23/50 ,  H01L23/3675 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8547 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A new method is provided for the establishment of a low resistivity connection between a wire bonded IC chip that is mounted on a heatsink and the heatsink of the package. A copper trace connection is allocated for this purpose on the surface of the substrate layer to which the IC chip is connected. An opening is provided in the substrate layer of the package, this opening aligns with the copper trace that has been allocated for establishing a ground connection and penetrates the substrate layer down to the surface of the underlying heatsink. The opening is filled with a conductive epoxy or an equivalent low-resistivity material thereby establishing a direct electrical connection or short between the allocated copper trace and the underlying heatsink. By connecting the ground point of the IC chip to the allocated copper trace, a direct electrical low resistivity connection is made between the ground point of the IC chip and the heatsink into which the IC chip is mounted.

公开(公告)号：US07977157B2

公开(公告)日：2011-07-12

申请号：US12715293

申请日：2010-03-01

Applicant: Setho Sing Fee ,  Lim Thiam Chye ,  Tongbi Jiang

Inventor： Setho Sing Fee ,  Lim Thiam Chye ,  Tongbi Jiang

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/66 ,  H01L21/44

CPC classification number: H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages.

Abstract translation: 一些实施例包括组装集成电路封装的方法，其中在半导体管芯的接合焊盘区域上形成至少两个不同的导电层，并且其中与插入件相关联的导电突起通过金球结合到 至少两个导电层。 导电层可以包括银，金，铜，铬，镍，钯，铂，钽，钛，钒和钨中的一种或多种。 在一些实施例中，接合焊盘区域可以包括铝，导电层的内部可以包括镍，导电层的外部可以包括金，与中介层相关联的导电突起可以包括金; 并且热超声键合可以包括插入物突起与金球的金 - 金结合，以及外导体层与金球的金 - 金结合。 一些实施例包括集成电路封装。

公开(公告)号：US20100224989A1

公开(公告)日：2010-09-09

申请号：US12782628

申请日：2010-05-18

Applicant: Setho Sing Fee

Inventor： Setho Sing Fee

IPC: H01L23/48 ,  H01L23/488 ,  H01L23/49

CPC classification number: H01L24/06 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/4951 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49433 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Microelectronic devices having intermediate contacts, and associated methods of packaging microelectronic devices with intermediate contacts, are disclosed herein. A packaged microelectronic device configured in accordance with one embodiment of the invention includes a microelectronic die attached to an interconnecting substrate. The microelectronic die includes an integrated circuit electrically coupled to a plurality of terminals. Each of the terminals is electrically coupled to a corresponding first contact on the die with an individual wire-bond. Each of the first contacts on the die is electrically coupled to a corresponding second contact on the interconnecting substrate by a conductive coupler such as a solder ball.

Abstract translation: 具有中间触点的微电子器件以及包含具有中间触点的微电子器件的相关方法在本文中公开。 根据本发明的一个实施例构造的封装的微电子器件包括附接到互连衬底的微电子管芯。 微电子管芯包括电耦合到多个端子的集成电路。 每个端子通过单独的引线接合电耦合到管芯上相应的第一接触。 管芯上的每个第一触点通过诸如焊球的导电耦合器电耦合到互连衬底上的对应的第二触点。

公开(公告)号：US07745944B2

公开(公告)日：2010-06-29

申请号：US11217629

申请日：2005-08-31

Applicant: Setho Sing Fee

Inventor： Setho Sing Fee

IPC: H01L23/52

CPC classification number: H01L24/06 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/4951 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49433 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Microelectronic devices having intermediate contacts, and associated methods of packaging microelectronic devices with intermediate contacts, are disclosed herein. A packaged microelectronic device configured in accordance with one embodiment of the invention includes a microelectronic die attached to an interconnecting substrate. The microelectronic die includes an integrated circuit electrically coupled to a plurality of terminals. Each of the terminals is electrically coupled to a corresponding first contact on the die with an individual wire-bond. Each of the first contacts on the die is electrically coupled to a corresponding second contact on the interconnecting substrate by a conductive coupler such as a solder ball.

Abstract translation: 具有中间触点的微电子器件以及包含具有中间触点的微电子器件的相关方法在本文中公开。 根据本发明的一个实施例构造的封装的微电子器件包括附接到互连衬底的微电子管芯。 微电子管芯包括电耦合到多个端子的集成电路。 每个端子通过单独的引线接合电耦合到管芯上相应的第一接触。 管芯上的每个第一触点通过诸如焊球的导电耦合器电耦合到互连衬底上的对应的第二触点。

公开(公告)号：US07183134B2

公开(公告)日：2007-02-27

申请号：US10931363

申请日：2004-08-31

Applicant: Teck Kheng Lee ,  Tan Yong Kian ,  Setho Sing Fee

Inventor： Teck Kheng Lee ,  Tan Yong Kian ,  Setho Sing Fee

IPC: H01L21/44

CPC classification number: H01L21/4832 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49503 ,  H01L23/49551 ,  H01L23/49558 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A circuit package is formed using a leadframe. The leadframe is formed or etched to align a plurality of bond pad structures above a reference plane while supporting leadframe fingers are positioned below the reference plane. Jumper wires are wirebonded between terminals on the die and the bond pads to form a package subassembly. The subassembly is encapsulated and then background to remove the leadframe fingers and surrounding frame. The bond pads which remain embedded in the encapsulation material are exposed on the lower surface of the package for connection to further conductors.

公开(公告)号：US07112876B2

公开(公告)日：2006-09-26

申请号：US11215619

申请日：2005-08-30

Applicant: Setho Sing Fee ,  Tay Wuu Yean ,  Lim Thiam Chye

Inventor： Setho Sing Fee ,  Tay Wuu Yean ,  Lim Thiam Chye

IPC: H01L23/02

CPC classification number: H01L24/97 ,  H01L21/4803 ,  H01L23/13 ,  H01L23/49811 ,  H01L24/45 ,  H01L24/48 ,  H01L24/50 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/181 ,  H05K3/0044 ,  H05K2203/0228 ,  H05K2203/1476 ,  Y10T408/03 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00

Abstract: An interposer includes a substantially planar substrate with a slot therethrough. The slot includes a laterally recessed area in only a portion of a periphery thereof at a location that exposes at least a portion of an active surface of the semiconductor die located between a bond pad and an outer periphery of the semiconductor die. The laterally recessed area may facilitate access to the bond pad by apparatus for forming, positioning, or securing intermediate conductive elements. The slot may be formed by forming a first, thin elongated slot through the interposer substrate, then widening a portion thereof. Alternatively, a first, small circular hole may be formed through the interposer substrate, and then an elongated slot having a width that exceeds the diameter of the small circular hole may be formed through the substrate at a location which is continuous with the small circular hole.

Abstract translation: 插入器包括具有穿过其中的槽的基本平坦的基板。 该槽在仅露出半导体管芯的有源表面的至少一部分的位置处仅在其周边的一部分中的侧向凹陷区域位于接合焊盘和半导体管芯的外周之间。 横向凹陷区域可以通过用于形成，定位或固定中间导电元件的装置来促进接合焊盘。 槽可以通过形成通过插入器基板的第一细长狭缝，然后加宽其一部分而形成。 或者，可以通过插入器基板形成第一小圆形孔，然后可以在与小圆孔连续的位置处形成具有超过小圆孔直径的宽度的细长槽 。

公开(公告)号：US06951982B2

公开(公告)日：2005-10-04

申请号：US10323150

申请日：2002-12-18

Applicant: Lim Thiam Chye ,  Setho Sing Fee ,  Eric Tan Swee Seng

Inventor： Lim Thiam Chye ,  Setho Sing Fee ,  Eric Tan Swee Seng

IPC: H01L25/10 ,  H01L23/02

CPC classification number: H01L25/105 ,  H01L24/97 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/3511 ,  Y10T29/49126 ,  Y10T29/49208 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00

Abstract: Various aspects of the invention provide microelectronic component assemblies, memory modules, computer systems, and methods of assembling microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a non-leaded first package, a second package, and a plurality of electrical junctions. The first package has a confronting surface that includes an exposed back surface of a microelectronic component and exposed contact surfaces. The second package has a confronting surface that includes an exposed back surface of a microelectronic component and exposed contact surfaces of a number of leads. Each of the junctions couples one of the contacts to the contact surface of one of the leads. The electrical junctions may also physically support the packages with their respective confronting surfaces juxtaposed with but spaced from one another, defining a peripherally open fluid passage and enhancing thermal performance.

Abstract translation: 本发明的各个方面提供微电子部件组件，存储器模块，计算机系统以及组装微电子部件组件的方法。 在一个具体实现中，微电子部件组件包括非引线第一封装，第二封装和多个电连接。 第一包装具有面对的表面，其包括微电子部件的暴露后表面和暴露的接触表面。 第二包装具有面对的表面，其包括微电子部件的暴露后表面和多个引线的暴露的接触表面。 每个连接点将触点中的一个耦合到其中一个引线的接触表面。 电接头还可以物理地支撑包装件，其各自的相对表面彼此并置但间隔开，限定了外围开放的流体通道并增强热性能。

公开(公告)号：US06951777B2

公开(公告)日：2005-10-04

申请号：US10837959

申请日：2004-05-03

Applicant: Setho Sing Fee ,  Tay Wuu Yean ,  Lim Thiam Chye

Inventor： Setho Sing Fee ,  Tay Wuu Yean ,  Lim Thiam Chye

IPC: H01L21/48 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H01L23/02

CPC classification number: H01L24/97 ,  H01L21/4803 ,  H01L23/13 ,  H01L23/49811 ,  H01L24/45 ,  H01L24/48 ,  H01L24/50 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/181 ,  H05K3/0044 ,  H05K2203/0228 ,  H05K2203/1476 ,  Y10T408/03 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00

Abstract: An interposer includes a substantially planar substrate with a slot formed therethrough. The slot includes a laterally recessed area formed in only a portion of a periphery thereof, which is positioned so as to expose at least a portion of an active surface of the semiconductor die located between a bond pad and an outer periphery of the semiconductor die. The laterally recessed area facilitates access to the bond pad by apparatus for forming, positioning, or securing intermediate conductive elements. The slot may be formed by forming a first, thin elongated slot through the interposer substrate, then widening a portion thereof. Alternatively, a first, small circular hole may be formed through the interposer substrate, then an elongated slot having a width that exceeds the diameter of the small circular hole may be formed through the substrate at a location which is continuous with the small circular hole.

Abstract translation: 插入器包括具有穿过其形成的狭槽的基本平坦的基板。 狭槽包括只形成在其周边的一部分中的横向凹入区域，其被定位成暴露位于半导体管芯的接合焊盘和外周之间的半导体管芯的有源表面的至少一部分。 横向凹陷区域便于通过用于形成，定位或固定中间导电元件的设备进入接合焊盘。 槽可以通过形成通过插入器基板的第一细长狭缝，然后加宽其一部分而形成。 或者，可以通过插入器基板形成第一小圆形孔，然后可以在与小圆孔连续的位置处形成具有超过小圆孔直径的宽度的细长槽。