公开(公告)号：US10236261B2

公开(公告)日：2019-03-19

申请号：US15492394

申请日：2017-04-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fang-Lin Tsai ,  Yi-Feng Chang ,  Lung-Yuan Wang

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L21/52 ,  H01L23/31 ,  H01L23/16 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: An electronic package is provided, which includes: a substrate; an electronic component and a shielding member disposed on the substrate; an encapsulant formed on the substrate and encapsulating the electronic component and the shielding member; and a metal layer formed on the encapsulant and electrically connected to the shielding member. A portion of a surface of the shielding member is exposed from a side surface of the encapsulant and in contact with the metal layer. As such, the width of the shielding member can be reduced so as to reduce the amount of solder paste used for bonding the shielding member to the substrate, thereby overcoming the conventional drawback of poor solder distribution. The present disclosure further provides a method for fabricating the electronic package.

公开(公告)号：US10163662B2

公开(公告)日：2018-12-25

申请号：US15478508

申请日：2017-04-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Cheng-Chia Chiang ,  Don-Son Jiang ,  Lung-Yuan Wang ,  Shih-Hao Tung ,  Shu-Huei Huang

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538

Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.

公开(公告)号：US09356008B2

公开(公告)日：2016-05-31

申请号：US14616013

申请日：2015-02-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Cheng-Chia Chiang ,  Hsin-Ta Lin ,  Fu-Tang Huang ,  Yu-Po Wang ,  Lung-Yuan Wang ,  Chu-Chi Hsu ,  Chia-Kai Shih

IPC: H01L25/16 ,  H01L25/00 ,  H01L23/00 ,  H01L23/42 ,  H01L23/31

CPC classification number: H01L25/162 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/562 ,  H01L23/564 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05015 ,  H01L2224/05016 ,  H01L2224/05078 ,  H01L2224/0519 ,  H01L2224/05561 ,  H01L2224/05582 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/06132 ,  H01L2224/06181 ,  H01L2224/11825 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1319 ,  H01L2224/13582 ,  H01L2224/13671 ,  H01L2224/1369 ,  H01L2224/1401 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/17517 ,  H01L2224/17519 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83101 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/0635 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/07025 ,  H01L2924/00

Abstract: A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls.

Abstract translation: 提供一种半导体封装，其包括：第一半导体器件，其具有第一顶表面和与第一顶表面相对的第一底表面; 形成在所述第一半导体器件的所述第一顶表面上的多个导电球; 具有第二顶表面和与第二顶表面相对的第二底表面的第二半导体器件; 以及形成在所述第二半导体器件的所述第二底表面上并相应地接合到所述导电球以用于电连接所述第一半导体器件和所述第二半导体器件的多个导电柱，其中所述导电柱的高度小于300μm。 因此，本发明可以容易地控制半导体封装的高度，并且可应用于具有细间距导电球的半导体封装。

公开(公告)号：US09343421B2

公开(公告)日：2016-05-17

申请号：US14309119

申请日：2014-06-19

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lung-Yuan Wang ,  Cheng-Chia Chiang ,  Chu-Chi Hsu ,  Chia-Kai Shih ,  Shu-Huei Huang

IPC: H01L33/00 ,  H01L23/00 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/19 ,  H01L24/73 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/29099 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor package is provided, which includes the steps of: providing a first substrate having a plurality of first conductive posts on a surface thereof and providing a second substrate having a third surface having a chip disposed thereon and a fourth surface opposite to the third surface; disposing the first substrate on the third surface of the second substrate through the first conductive posts; forming an encapsulant between the first substrate and the second substrate, wherein the encapsulant has a first surface adjacent to the first substrate and a second surface opposite to the first surface; and removing the first substrate, thereby effectively preventing solder bridging from occurring.

Abstract translation: 提供一种制造半导体封装的方法，其包括以下步骤：提供在其表面上具有多个第一导电柱的第一衬底，并提供第二衬底，该第二衬底具有设置在其上的芯片的第三表面和与其相对的第四表面 到第三面; 通过第一导电柱将第一衬底设置在第二衬底的第三表面上; 在所述第一基板和所述第二基板之间形成密封剂，其中所述密封剂具有与所述第一基板相邻的第一表面和与所述第一表面相对的第二表面; 并移除第一基板，从而有效地防止焊料桥接发生。

公开(公告)号：US20150200169A1

公开(公告)日：2015-07-16

申请号：US14309119

申请日：2014-06-19

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lung-Yuan Wang ,  Cheng-Chia Chiang ,  Chu-Chi Hsu ,  Chia-Kai Shih ,  Shu-Huei Huang

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/19 ,  H01L24/73 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/29099 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor package is provided, which includes the steps of: providing a first substrate having a plurality of first conductive posts on a surface thereof and providing a second substrate having a third surface having a chip disposed thereon and a fourth surface opposite to the third surface; disposing the first substrate on the third surface of the second substrate through the first conductive posts; forming an encapsulant between the first substrate and the second substrate, wherein the encapsulant has a first surface adjacent to the first substrate and a second surface opposite to the first surface; and removing the first substrate, thereby effectively preventing solder bridging from occurring.

Abstract translation: 提供一种制造半导体封装的方法，其包括以下步骤：提供在其表面上具有多个第一导电柱的第一衬底，并提供第二衬底，该第二衬底具有设置在其上的芯片的第三表面和与其相对的第四表面 到第三面; 通过第一导电柱将第一衬底设置在第二衬底的第三表面上; 在所述第一基板和所述第二基板之间形成密封剂，其中所述密封剂具有与所述第一基板相邻的第一表面和与所述第一表面相对的第二表面; 并移除第一基板，从而有效地防止焊料桥接发生。

公开(公告)号：US20150187741A1

公开(公告)日：2015-07-02

申请号：US14211244

申请日：2014-03-14

Applicant: Siliconware Precision Industries Co., Ltd

Inventor： Shih-Hao Tung ,  Chang-Yi Lan ,  Lung-Yuan Wang ,  Cheng-Chia Chiang ,  Chu-Huei Huang

IPC: H01L25/10 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/207

Abstract: A method for fabricating a package on package (PoP) structure is provided, which includes: providing a first packaging substrate having at least a first electronic element and a plurality of first support portions, wherein the first electronic element is electrically connected to the first packaging substrate; forming an encapsulant on the first packaging substrate for encapsulating the first electronic element and the first support portions; forming a plurality of openings in the encapsulant for exposing portions of surfaces of the first support portions; and providing a second packaging substrate having a plurality of second support portions and stacking the second packaging substrate on the first packaging substrate with the second support portions positioned in the openings of the encapsulant and bonded with the first support portions. As such, the encapsulant effectively separates the first support portions or the second support portions from one another to prevent bridging from occurring therebetween.

Abstract translation: 提供了一种用于制造封装（PoP）封装结构的方法，其包括：提供具有至少第一电子元件和多个第一支撑部分的第一封装基板，其中第一电子元件电连接到第一封装 基质; 在所述第一包装基板上形成密封剂，以密封所述第一电子元件和所述第一支撑部分; 在所述密封剂中形成多个开口以暴露所述第一支撑部分的表面的部分; 以及提供具有多个第二支撑部分的第二包装基板，并且将第二包装基板堆叠在第一包装基板上，其中第二支撑部分位于密封剂的开口中并与第一支撑部分结合。 因此，密封剂有效地将第一支撑部分或第二支撑部分彼此分离，以防止在它们之间发生桥接。

公开(公告)号：US20150187722A1

公开(公告)日：2015-07-02

申请号：US14255326

申请日：2014-04-17

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Cheng-Chia Chiang ,  Don-Son Jiang ,  Lung-Yuan Wang ,  Shih-Hao Tung ,  Shu-Huei Huang

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.

Abstract translation: 提供一种半导体封装，其包括：具有相对的第一和第二表面的封装基板和形成在第一表面上的多个第一和第二导电焊盘; 具有相反的有源和无源表面的芯片，并经由其主动表面设置在第一导电焊盘上; 分别形成在所述第二导电焊盘上的多个导电柱; 以及形成在所述封装基板的所述第一表面上的第一密封剂，用于封装所述芯片和所述导电柱，并且具有用于暴露所述导电柱的上表面的多个开口，从而增加所述封装密度并保护所述芯片和所述互连结构 受到水分侵入的不利影响。

公开(公告)号：US20240162140A1

公开(公告)日：2024-05-16

申请号：US18389105

申请日：2023-11-13

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Feng Kao ,  Lung-Yuan Wang

IPC: H01L23/522 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5226 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L23/31 ,  H01L24/14

Abstract: An electronic package is provided, in which an electronic structure used as an integrated voltage regulator and a plurality of conductive pillars are embedded in an encapsulating layer to facilitate electrical transmission with electronic components at a close range.

公开(公告)号：US20230420391A1

公开(公告)日：2023-12-28

申请号：US17944453

申请日：2022-09-14

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Feng Kao ,  Lung-Yuan Wang

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  G02B6/12 ,  G02B6/13

CPC classification number: H01L23/564 ,  H01L23/49811 ,  H01L23/3185 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L21/563 ,  G02B6/12 ,  G02B6/13 ,  H01L23/49827 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  G02B2006/121

Abstract: An electronic package is provided, in which an electronic element that is electrically connected to a plurality of conductive vias and a functional part that has a hollow area are disposed on a photonic die that has the plurality of conductive vias and at least one external connection portion, where a cladding layer covers the electronic element and the functional part, such that the external connection portion is exposed from the hollow area and the cladding layer for an optical fiber to insert into the hollow area and connect to the external connection portion, so as to achieve the purpose of optoelectronic integration.

公开(公告)号：US20230369229A1

公开(公告)日：2023-11-16

申请号：US17858358

申请日：2022-07-06

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Hsin-Jou Lin ,  Lung-Yuan Wang ,  Chih-Nan Lin ,  Feng Kao ,  Chiu-Ling Chen

IPC: H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L25/105 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5386 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/49838 ,  H01L23/5385 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/3512 ,  H01L2924/182

Abstract: An electronic package and manufacturing method thereof are provided, in which an electronic module served as a bridge element and a plurality of conductive pillars are embedded in a packaging layer, a routing structure is formed on the packaging layer, and a plurality of electronic elements are disposed on the routing structure, such that the electronic elements electrically bridge the electronic module via the routing structure.