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29 条记录 (耗时 0.021 秒)

    Method of making a metal-insulator-metal capacitor in the CMOS process
    21.
    发明授权
    Method of making a metal-insulator-metal capacitor in the CMOS process 有权
    在CMOS工艺中制作金属 - 绝缘体 - 金属电容器的方法

    公开(公告)号：US07294544B1

    公开(公告)日：2007-11-13

    申请号：US09249254

    申请日：1999-02-12

    申请人： Yen-Shih Ho ,  Jau-Yuann Chung ,  Chun-Hon Chen ,  Hun-Jan Tao

    发明人： Yen-Shih Ho ,  Jau-Yuann Chung ,  Chun-Hon Chen ,  Hun-Jan Tao

    IPC分类号： H01L21/336

    CPC分类号： H01L21/8221 ,  H01L23/5223 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating an improved metal-insulator-metal capacitor is achieved. An insulating layer is provided overlying conducting lines on a semiconductor substrate. Via openings through the insulating layer to the conducting lines are filled with metal plugs. A first metal layer is deposited overlying the insulating layer and the metal plugs. A capacitor dielectric layer is deposited overlying the first metal layer wherein capacitor dielectric layer is deposited as a dual layer, each layer deposited within a separate chamber whereby pinholes are eliminated. A second metal layer and a barrier metal layer are deposited overlying the capacitor dielectric layer. The second metal layer and the barrier metal layer are patterned to form a top plate electrode. Thereafter, the capacitor dielectric layer and the first metal layer are patterned to form a bottom plate electrode completing fabrication of a metal-insulator-metal capacitor.

    摘要翻译： 实现了一种制造改进的金属 - 绝缘体 - 金属电容器的方法。 在半导体衬底上覆盖导电线的绝缘层。 通过绝缘层到导线的开口填充有金属插头。 沉积在绝缘层和金属插头上的第一金属层。 电容器电介质层沉积在第一金属层上，其中电容器电介质层被沉积为双层，每层沉积在单独的室内，由此消除针孔。 沉积在电容器介电层上的第二金属层和阻挡金属层。 将第二金属层和阻挡金属层图案化以形成顶板电极。 此后，对电容器电介质层和第一金属层进行图案化以形成完成金属 - 绝缘体 - 金属电容器的制造的底板电极。

    Uniform sidewall profile etch method for forming low contact leakage schottky diode contact
    22.
    发明授权
    Uniform sidewall profile etch method for forming low contact leakage schottky diode contact 有权

    公开(公告)号：US6096629A

    公开(公告)日：2000-08-01

    申请号：US187301

    申请日：1998-11-05

    申请人： Jun-Lin Tsai ,  Yen-Shih Ho

    发明人： Jun-Lin Tsai ,  Yen-Shih Ho

    IPC分类号： H01L21/285 ,  H01L21/311 ,  H01L21/768 ,  H01L21/28

    CPC分类号： H01L21/28537 ,  H01L21/31116 ,  H01L21/76804

    摘要： A method for forming a Schottky diode. There is first provided a silicon layer. There is then formed upon the silicon layer an anisotropically patterned first dielectric layer which defines a Schottky diode contact region of the silicon layer. There is then formed and aligned upon the anisotropically patterned first dielectric layer a patterned second dielectric layer which is formed of a thermally reflowable material. There is then reflowed thermally the patterned second dielectric layer to form a thermally reflowed patterned second dielectric layer having a uniform sidewall profile with respect to the anisotropically patterned first dielectric layer while simultaneously forming a thermal silicon oxide layer upon the Schottky diode contact region of the silicon layer. There is then etched while employing a first etch method the thermal silicon oxide layer from the Schottky diode contact region of the silicon layer while preserving the uniform sidewall profile of the thermally reflowed patterned second dielectric layer with respect to the anisotropically patterned first dielectric layer. There is then formed and thermally annealed upon the thermally reflowed patterned second dielectric layer and the Schottky diode contact region of the silicon layer a metal silicide forming metal layer to form in a self aligned fashion a metal silicide layer upon the Schottky diode contact region of the silicon layer, a protective oxide surface layer upon the metal silicide layer and a metal silicide forming metal layer residue upon the thermally reflowed patterned second dielectric layer. There is then stripped from the thermally reflowed patterned second dielectric layer the metal silicide forming metal layer residue. Finally, there is then etched while employing a second etch method the protective oxide surface layer from the metal silicide layer, where the second etch method also preserves the uniform sidewall profile of the thermally reflowed patterned second dielectric layer with respect to the anisotropically patterned first dielectric layer.

    Chip package
    24.
    发明授权
    Chip package 有权
    芯片封装

    公开(公告)号：US08779452B2

    公开(公告)日：2014-07-15

    申请号：US13224267

    申请日：2011-09-01

    申请人： Tzu-Hsiang Hung ,  Hsin-Chih Chiu ,  Chuan-Jin Shiu ,  Chia-Sheng Lin ,  Yen-Shih Ho ,  Yu-Min Liang

    发明人： Tzu-Hsiang Hung ,  Hsin-Chih Chiu ,  Chuan-Jin Shiu ,  Chia-Sheng Lin ,  Yen-Shih Ho ,  Yu-Min Liang

    IPC分类号： H01L29/22

    CPC分类号： H01L27/14618 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2933/0066 ,  H01L2924/014 ,  H01L2924/00

    摘要： An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device disposed at the first surface; a protection layer disposed on the second surface of the substrate, wherein the protection layer has an opening; a conducting bump disposed on the second surface of the substrate and filled in the opening; a conducting layer disposed between the protection layer and the substrate, wherein the conducting layer electrically connects the optoelectronic device to the conducting bump; and a light shielding layer disposed on the protection layer, wherein the light shielding layer does not contact with the conducting bump.

    摘要翻译： 本发明的实施例提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 设置在第一表面处的光电子器件; 保护层，设置在所述基板的第二表面上，其中所述保护层具有开口; 设置在所述基板的第二表面上并填充在所述开口中的导电凸块; 设置在所述保护层和所述基板之间的导电层，其中所述导电层将所述光电子器件电连接到所述导电凸块; 以及设置在保护层上的遮光层，其中遮光层不与导电凸块接触。

    Method for manufacturing a silicide to silicide capacitor
    28.
    发明授权
    Method for manufacturing a silicide to silicide capacitor 失效
    硅化物电容器的制造方法

    公开(公告)号：US6051475A

    公开(公告)日：2000-04-18

    申请号：US089558

    申请日：1998-06-03

    申请人： Yen-Shih Ho ,  Chun-Hon Chen

    发明人： Yen-Shih Ho ,  Chun-Hon Chen

    IPC分类号： H01L21/02 ,  H01L21/28

    CPC分类号： H01L28/40 ,  H01L28/60

    摘要： A process is described for the manufacture of a capacitor having low V.sub.cc. Said process is fully compatible with standard IC manufacturing and introduces minimum modification thereto. The process involves the formation of a capacitor having both upper and lower electrodes that comprise layers of a metal silicide. The lower electrode is formed as a byproduct of the SALICIDE process while the upper electrode is formed by first laying down a layer of polysilicon followed by a layer of a silicide-forming metal such as titanium, cobalt, or tungsten. Sufficient of the metal must be provided to ensure that all of the polysilicon gets transformed to silicide.

    摘要翻译： 描述了制造具有低Vcc的电容器的工艺。 所述方法与标准IC制造完全兼容，并对其进行最小修改。 该方法包括形成具有包括金属硅化物层的上电极和下电极的电容器。 下电极形成为SALICIDE工艺的副产物，而上电极通过首先铺设多晶硅层，然后形成诸如钛，钴或钨的硅化物形成金属层而形成。 必须提供足够的金属以确保所有的多晶硅转变为硅化物。

    Method of increasing end point detection capability of reactive ion etching by adding pad area
    29.
    发明授权
    Method of increasing end point detection capability of reactive ion etching by adding pad area 失效
    通过添加焊盘面积增加反应离子蚀刻终点检测能力的方法

    公开(公告)号：US6004829A

    公开(公告)日：1999-12-21

    申请号：US928229

    申请日：1997-09-12

    申请人： Tzong-Sheng Chang ,  Yen-Shih Ho ,  Ruey-Hsin Liou ,  Yuan-Cheng Yu

    发明人： Tzong-Sheng Chang ,  Yen-Shih Ho ,  Ruey-Hsin Liou ,  Yuan-Cheng Yu

    IPC分类号： H01L21/311 ,  H01L21/66 ,  H01L21/8247 ,  H01L23/544 ,  H01L21/8238

    CPC分类号： H01L27/11526 ,  H01L21/31116 ,  H01L22/26 ,  H01L22/34 ,  H01L27/11539 ,  H01L2924/0002

    摘要： A method of forming a semiconductor device includes forming of layers of polysilicon and dielectric layers in manufacturing a semiconductor device and patterning the layers into devices using phototlithography and etching process steps. End point mode detection is used in the etching process in a way in which the area exposed during etching is increased to enhance the end point detection capacity, by adding a surplus pad area before pad formation. Specifically an EPROM device is formed with a first level of polysilicon above a gate oxide layer patterned into a floating gate electrode of an EPROM device. Then form an ONO layer above the floating gate electrode. Define array protection, grow a second gate oxide layer, deposit a second level of polysilicon, define peripheral gates from the second level of polysilicon, and define an EPROM transistor gate electrode from the second level of polysilicon.

    摘要翻译： 形成半导体器件的方法包括在制造半导体器件中形成多晶硅层和电介质层，并使用光刻和蚀刻工艺步骤将层图案化成器件。 在蚀刻工艺中使用端点模式检测，其中通过在焊盘形成之前添加剩余焊盘区域，在蚀刻期间暴露的区域增加以增强端点检测能力的方式。 具体地说，EPROM器件形成有图案化为EPROM器件的浮置栅电极的栅极氧化物层上方的第一级多晶硅。 然后在浮栅电极上形成ONO层。 定义阵列保护，生长第二栅极氧化层，沉积第二级多晶硅，从第二级多晶硅定义外围栅极，并从第二级多晶硅定义EPROM晶体管栅电极。