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    Terminal structure, and semiconductor element and module substrate comprising the same
    21.
    发明授权
    Terminal structure, and semiconductor element and module substrate comprising the same 有权

    公开(公告)号：US09224706B2

    公开(公告)日：2015-12-29

    申请号：US13960330

    申请日：2013-08-06

    Applicant: TDK CORPORATION

    Inventor： Kenichi Yoshida ,  Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

    IPC: H01L23/48 ,  H01L23/00

    Abstract: A preferred terminal structure comprises a base material; an electrode formed on the base material; an insulating covering layer formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under bump metal layer containing Ni, formed in a region in the opening on the electrode so that an upper surface of the metal layer is at a position lower than an upper surface of the insulating covering layer in a peripheral edge portion of the opening; and a dome-shaped bump containing Sn and Ti, formed in a region in the opening on the under bump metal layer, wherein an end portion of a boundary between the under bump metal layer and the bump is in contact with an inner wall of the opening portion in the insulating covering layer.

    Coating and electronic component
    23.
    发明授权
    Coating and electronic component 有权
    涂料和电子元件

    公开(公告)号：US08933336B2

    公开(公告)日：2015-01-13

    申请号：US13678033

    申请日：2012-11-15

    Applicant: TDK Corporation

    Inventor： Kenichi Yoshida ,  Yuhei Horikawa ,  Makoto Orikasa ,  Hideyuki Seike

    IPC: H01B1/00 ,  H01B1/02

    CPC classification number: H01B1/02 ,  H01L2224/85444

    Abstract: A coating having a layered structure including a palladium layer is provided to a conductor. The highly stable palladium layer is amorphous and contains phosphorus in a concentration ranging from 7.3% by mass to 11.0% by mass. An electronic component may include the conductor coated with the coating. The conductor coated with the coating has superior corrosion resistance and superior reliability in electrical connection with external apparatuses.

    Abstract translation: 具有包括钯层的层状结构的涂层被提供给导体。 高度稳定的钯层为无定形，含有浓度为7.3质量％〜11.0质量％的磷。 电子部件可以包括涂覆有涂层的导体。 涂覆有涂层的导体具有优异的耐腐蚀性和与外部设备电连接的优异的可靠性。

    Coil component and wireless communication circuit using the same
    25.
    发明授权
    Coil component and wireless communication circuit using the same 有权

    公开(公告)号：US11804654B2

    公开(公告)日：2023-10-31

    申请号：US17403575

    申请日：2021-08-16

    Applicant: TDK Corporation

    Inventor： Masaki Matsushima ,  Makoto Orikasa ,  Ryota Uchiyama ,  Junpei Hayama

    IPC: H01Q1/36 ,  H01Q7/00 ,  H01Q1/38

    CPC classification number: H01Q7/00 ,  H01Q1/38

    Abstract: Disclosed herein is a coil component that includes a substrate, a coil pattern formed on one surface of the substrate, and a magnetic layer comprising a composite material obtained by dispersing magnetic particles in resin and formed on the one surface of the substrate so as to cover the coil pattern. The coil pattern has a flat shape in which a thickness thereof is smaller than a radial width. Each of the magnetic particles has a flat shape in which a thickness thereof in a direction perpendicular to the one surface of the substrate is smaller than a diameter in a direction parallel to the one surface of the substrate. Some of the magnetic particles exist within a height range of the coil pattern with respect to the one surface of the substrate.

    Method for producing semiconductor chip
    27.
    发明授权
    Method for producing semiconductor chip 有权

    公开(公告)号：US10354973B2

    公开(公告)日：2019-07-16

    申请号：US16037537

    申请日：2018-07-17

    Applicant: TDK CORPORATION

    Inventor： Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

    IPC: H01L21/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

    Abstract: A method for producing a semiconductor chip is a method for producing a semiconductor chip that includes a substrate, a conductive portion formed on the substrate, and a microbump formed on the conductive portion, which includes a smooth surface formation process of forming a smooth surface on the microbump, and the smooth surface formation process includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump and among principal surfaces of the pressure application member, a principal surface that contacts the microbump is a flat surface.

    Method for producing semiconductor package
    28.
    发明授权
    Method for producing semiconductor package 有权

    公开(公告)号：US10163847B2

    公开(公告)日：2018-12-25

    申请号：US15449361

    申请日：2017-03-03

    Applicant: TDK CORPORATION

    Inventor： Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

    IPC: H01L21/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

    Abstract: A method for producing a semiconductor package is a method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on the substrate, and microbumps formed on the conductive portions, are laminated, which includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump.

    WIRING COMPONENT
    29.
    发明申请
    WIRING COMPONENT 审中-公开

    公开(公告)号：US20180175494A1

    公开(公告)日：2018-06-21

    申请号：US15840192

    申请日：2017-12-13

    Applicant: TDK Corporation

    Inventor： Yuhei Horikawa ,  Makoto Orikasa ,  Yoshihiro Kanbayashi ,  Hisayuki Abe ,  Hirohumi Asou ,  Kosuke Kunitsuka

    IPC: H01Q1/38 ,  H01Q1/22 ,  H01Q7/00

    CPC classification number: H01Q1/38 ,  H01Q1/2208 ,  H01Q1/2225 ,  H01Q7/00 ,  H04B5/0031 ,  H04B5/0081

    Abstract: Disclosed herein is a wiring component that includes a base material and a planar coil pattern formed on the base material. The planar coil pattern includes a coil wiring portion having one end, other end, and first to third connecting positions, the second connecting position being closer to the other end compared with the first connecting position, the third connecting position being closer to the one end compared with the second connecting position; a power-feed wiring portion connected to the first connecting position; and a connection wiring portion that short-circuits the second connecting position and the third connecting position. A cross-section structure of the planar coil pattern has a base resin layer formed on the base material, and a conductive layer formed on the base resin layer.

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