公开(公告)号：US10294098B2

公开(公告)日：2019-05-21

申请号：US15855449

申请日：2017-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Hua Lin ,  Chang-Ming Wu ,  Chung-Yi Yu ,  Ping-Yin Liu ,  Jung-Huei Peng

IPC: B81B7/00 ,  B81C1/00 ,  H01L23/00

Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.

公开(公告)号：US10147794B2

公开(公告)日：2018-12-04

申请号：US15332115

申请日：2016-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L29/788 ,  H01L29/423 ,  H01L27/11521 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11568 ,  H01L29/51

Abstract: The present disclosure relates to a split gate memory device. In some embodiments, the split gate memory device includes a memory gate arranged over a substrate, and a select gate arranged over the substrate. An inter-gate dielectric layer is arranged between sidewalls of the memory gate and the select gate that face one another. The inter-gate dielectric layer extends under the memory gate. A first dielectric is disposed above the inter-gate dielectric layer and is arranged between the sidewalls of the memory gate and the select gate.

公开(公告)号：US10037893B1

公开(公告)日：2018-07-31

申请号：US15464541

申请日：2017-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lee-Chuan Tseng ,  Chang-Ming Wu

IPC: H01L21/31 ,  H01L21/311 ,  H01L21/67 ,  H01L21/677

CPC classification number: H01L21/31116 ,  H01L21/3065 ,  H01L21/67069 ,  H01L21/67739

Abstract: A method and apparatus for etching a wafer are provided. The method includes placing a first wafer with a first target material into a first chamber, and placing a second wafer with a second target material into a second chamber. The second chamber is connected to the first chamber by a first pipe. The method also includes applying a first Xe-containing gaseous etchant into the first chamber to etch the first target material. A portion of the first Xe-containing gaseous etchant in the first chamber is unreacted during the etching of the first target material. The method further includes applying the unreacted portion of the first Xe-containing gaseous etchant from the first chamber into the second chamber through the first pipe to etch the second target material of the second wafer.

公开(公告)号：US10029910B1

公开(公告)日：2018-07-24

申请号：US15447711

申请日：2017-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lee-Chuan Tseng ,  Chang-Ming Wu

IPC: B81C1/00 ,  B81B7/00

Abstract: Structures and formation methods of a MEMS device structure are provided. The MEMS device structure includes a semiconductor substrate having a first region and a second region, and a MEMS layer over the semiconductor substrate. The MEMS layer has a first through hole positioned in the first region and a second through hole positioned in the second region. The MEMS device structure also includes a cap layer over the MEMS layer, a first cavity between the semiconductor substrate and the cap layer and in the first region, and a second cavity between the semiconductor substrate and the cap layer and in the second region. The MEMS device structure further includes a carbon-based degradation product in the first cavity.

公开(公告)号：US09748255B2

公开(公告)日：2017-08-29

申请号：US14276340

申请日：2014-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee

IPC: H01L29/788 ,  H01L21/336 ,  H01L27/11521 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: Some embodiments of the present disclosure relate to a memory device, which includes a floating gate formed over a channel region of a substrate, and a control gate formed over the floating gate. First and second spacers are formed along sidewalls of the control gate, and extend over outer edges of the floating gate to form a non-uniform overhang, which can induce a wide distribution of erase speeds of the memory device. To improve the erase speed distribution, an etching process is performed on the first and second spacers prior to erase gate formation. The etching process removes the overhang of the first and second spacers at an interface between a bottom region of the first and second spacers and a top region of the floating gate to form a planar surface at the interface, and improves the erase speed distribution of the memory device.

公开(公告)号：US09741868B2

公开(公告)日：2017-08-22

申请号：US14688011

申请日：2015-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/78 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L27/1157

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/66833 ,  H01L29/7831

Abstract: The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has a memory gate with a flat top surface. A memory gate spacer is arranged directly above the memory gate having a lateral dimension smaller than that of the memory gate. The memory gate spacer has an inner sidewall disposed along an upper portion of a charge trapping layer and an outer sidewall recessed back laterally relative to an outer sidewall of the memory gate. In some embodiments, a dielectric liner is continuously lined the outer sidewall of the memory gate, extending on a portion of the top surface of the memory gate not covered by the memory gate spacer, and extending upwardly along the outer sidewall of the memory gate spacer.

公开(公告)号：US09741728B2

公开(公告)日：2017-08-22

申请号：US15245539

申请日：2016-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/788 ,  H01L27/11521 ,  H01L27/11541 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11526 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/3215 ,  H01L27/11531

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/32139 ,  H01L21/32155 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11541 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

Abstract: A method of manufacturing an embedded flash memory device is provided. A pair of gate stacks are formed spaced over a semiconductor substrate, and including floating gates and control gates over the floating gates. A common gate layer is formed over the gate stacks and the semiconductor substrate, and lining sidewalls of the gate stacks. A first etch is performed into the common gate layer to recess an upper surface of the common gate layer to below upper surfaces respectively of the gate stacks, and to form an erase gate between the gate stacks. Hard masks are respectively formed over the erase gate, a word line region of the common gate layer, and a logic gate region of the common gate layer. A second etch is performed into the common gate layer with the hard masks in place to concurrently form a word line and a logic gate.

公开(公告)号：US20170162590A1

公开(公告)日：2017-06-08

申请号：US15438907

申请日：2017-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Chin-Yi Huang ,  Shih-Chang Liu ,  Chang-Ming Wu

IPC: H01L27/11534 ,  H01L27/11521 ,  H01L29/66

CPC classification number: H01L27/11534 ,  H01L27/11521 ,  H01L29/66545

Abstract: The present disclosure relates to an integrated circuit (IC). The IC includes a substrate, which includes a periphery region having a first substrate surface and a memory cell region having a second substrate surface. The second substrate surface is recessed within the substrate relative to the first substrate surface. A high k metal gate (HKMG) transistor is disposed on the first substrate surface and includes a HKMG gate. Two neighboring flash memory cells are disposed on the second substrate surface and include a pair of flash memory cell control gates. Top surfaces of the HKMG gate and flash memory cell control gates are co-planar.

公开(公告)号：US20170125434A1

公开(公告)日：2017-05-04

申请号：US15408994

申请日：2017-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Min ,  Tsung-Hsueh Yang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/11568 ,  H01L29/423 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/321 ,  H01L29/792 ,  H01L21/768 ,  H01L21/311 ,  H01L21/265 ,  H01L29/66 ,  H01L29/08 ,  H01L21/28 ,  H01L21/3105

CPC classification number: H01L27/11568 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/26513 ,  H01L21/28282 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/32139 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. In some embodiments, a semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.

公开(公告)号：US09614048B2

公开(公告)日：2017-04-04

申请号：US14306726

申请日：2014-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/423 ,  H01L29/788 ,  H01L29/66 ,  H01L21/28 ,  H01L29/417 ,  H01L27/11524

CPC classification number: H01L29/42368 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/41725 ,  H01L29/42328 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7883 ,  H01L2924/1438

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a source region and a drain region. Further, the semiconductor structure includes a floating gate, a word line, and an erase gate located over the semiconductor substrate between the source and drain regions. The floating gate is arranged between the word line and the erase gate. Even more, the semiconductor structure includes a dielectric disposed between the erase and floating gates. A thickness of the dielectric between the erase and floating gates is variable and increases towards the semiconductor substrate. A method of manufacturing the semiconductor structure is also provided.