公开(公告)号：US09748255B2

公开(公告)日：2017-08-29

申请号：US14276340

申请日：2014-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee

IPC: H01L29/788 ,  H01L21/336 ,  H01L27/11521 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: Some embodiments of the present disclosure relate to a memory device, which includes a floating gate formed over a channel region of a substrate, and a control gate formed over the floating gate. First and second spacers are formed along sidewalls of the control gate, and extend over outer edges of the floating gate to form a non-uniform overhang, which can induce a wide distribution of erase speeds of the memory device. To improve the erase speed distribution, an etching process is performed on the first and second spacers prior to erase gate formation. The etching process removes the overhang of the first and second spacers at an interface between a bottom region of the first and second spacers and a top region of the floating gate to form a planar surface at the interface, and improves the erase speed distribution of the memory device.

公开(公告)号：US09741868B2

公开(公告)日：2017-08-22

申请号：US14688011

申请日：2015-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/78 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L27/1157

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/66833 ,  H01L29/7831

Abstract: The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has a memory gate with a flat top surface. A memory gate spacer is arranged directly above the memory gate having a lateral dimension smaller than that of the memory gate. The memory gate spacer has an inner sidewall disposed along an upper portion of a charge trapping layer and an outer sidewall recessed back laterally relative to an outer sidewall of the memory gate. In some embodiments, a dielectric liner is continuously lined the outer sidewall of the memory gate, extending on a portion of the top surface of the memory gate not covered by the memory gate spacer, and extending upwardly along the outer sidewall of the memory gate spacer.

公开(公告)号：US09741728B2

公开(公告)日：2017-08-22

申请号：US15245539

申请日：2016-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/788 ,  H01L27/11521 ,  H01L27/11541 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11526 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/3215 ,  H01L27/11531

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/32139 ,  H01L21/32155 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11541 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

Abstract: A method of manufacturing an embedded flash memory device is provided. A pair of gate stacks are formed spaced over a semiconductor substrate, and including floating gates and control gates over the floating gates. A common gate layer is formed over the gate stacks and the semiconductor substrate, and lining sidewalls of the gate stacks. A first etch is performed into the common gate layer to recess an upper surface of the common gate layer to below upper surfaces respectively of the gate stacks, and to form an erase gate between the gate stacks. Hard masks are respectively formed over the erase gate, a word line region of the common gate layer, and a logic gate region of the common gate layer. A second etch is performed into the common gate layer with the hard masks in place to concurrently form a word line and a logic gate.

公开(公告)号：US20170162590A1

公开(公告)日：2017-06-08

申请号：US15438907

申请日：2017-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Chin-Yi Huang ,  Shih-Chang Liu ,  Chang-Ming Wu

IPC: H01L27/11534 ,  H01L27/11521 ,  H01L29/66

CPC classification number: H01L27/11534 ,  H01L27/11521 ,  H01L29/66545

Abstract: The present disclosure relates to an integrated circuit (IC). The IC includes a substrate, which includes a periphery region having a first substrate surface and a memory cell region having a second substrate surface. The second substrate surface is recessed within the substrate relative to the first substrate surface. A high k metal gate (HKMG) transistor is disposed on the first substrate surface and includes a HKMG gate. Two neighboring flash memory cells are disposed on the second substrate surface and include a pair of flash memory cell control gates. Top surfaces of the HKMG gate and flash memory cell control gates are co-planar.

公开(公告)号：US20170125434A1

公开(公告)日：2017-05-04

申请号：US15408994

申请日：2017-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Min ,  Tsung-Hsueh Yang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/11568 ,  H01L29/423 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/321 ,  H01L29/792 ,  H01L21/768 ,  H01L21/311 ,  H01L21/265 ,  H01L29/66 ,  H01L29/08 ,  H01L21/28 ,  H01L21/3105

CPC classification number: H01L27/11568 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/26513 ,  H01L21/28282 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/32139 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. In some embodiments, a semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.

公开(公告)号：US09614048B2

公开(公告)日：2017-04-04

申请号：US14306726

申请日：2014-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/423 ,  H01L29/788 ,  H01L29/66 ,  H01L21/28 ,  H01L29/417 ,  H01L27/11524

CPC classification number: H01L29/42368 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/41725 ,  H01L29/42328 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7883 ,  H01L2924/1438

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a source region and a drain region. Further, the semiconductor structure includes a floating gate, a word line, and an erase gate located over the semiconductor substrate between the source and drain regions. The floating gate is arranged between the word line and the erase gate. Even more, the semiconductor structure includes a dielectric disposed between the erase and floating gates. A thickness of the dielectric between the erase and floating gates is variable and increases towards the semiconductor substrate. A method of manufacturing the semiconductor structure is also provided.

公开(公告)号：US09589976B2

公开(公告)日：2017-03-07

申请号：US14688201

申请日：2015-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/788 ,  H01L29/423 ,  H01L27/12 ,  H01L27/01 ,  H01L27/115 ,  H01L21/28 ,  H01L23/48 ,  H01L29/88 ,  H01L21/306

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L21/30625 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/42344

Abstract: The present disclosure relates to an integrated circuit (IC), including, a flash memory device region, including a pair of split-gate flash memory cells arranged over a semiconductor substrate. The pair of split gate flash memory cells respectively have a control gate (CG) including a polysilicon gate and an overlying silicide layer. A periphery circuit including, one or more high-k metal gate (HKMG) transistors are arranged over the semiconductor substrate at a position laterally offset from the flash memory device region. The one or more HKMG transistors have a metal gate electrode with an upper surface that is lower than an upper surface of the silicide layer. A method of manufacturing the IC is also provided.

Abstract translation: 本公开涉及一种集成电路（IC），其包括闪存器件区域，其包括布置在半导体衬底上的一对分裂栅极闪存单元。 一对分裂栅极闪存单元分别具有包括多晶硅栅极和上覆硅化物层的控制栅极（CG）。 包括一个或多个高k金属栅极（HKMG）晶体管的外围电路在横向偏离闪存器件区域的位置上布置在半导体衬底的上方。 一个或多个HKMG晶体管具有金属栅电极，其上表面低于硅化物层的上表面。 还提供了一种制造IC的方法。

公开(公告)号：US09570457B2

公开(公告)日：2017-02-14

申请号：US14468410

申请日：2014-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Min ,  Tsung-Hsueh Yang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/423

CPC classification number: H01L27/11568 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/26513 ,  H01L21/28282 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/32139 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. A semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.

Abstract translation: 提供了具有非对称轮廓的硬掩模的分裂栅极闪存单元器件的半导体结构。 半导体结构的半导体衬底包括第一源极/漏极区域和第二源极/漏极区域。 半导体结构的控制栅极和存储栅极在第一和第二源极/漏极区之间的半导体衬底上间隔开。 半导体结构的电荷捕获电介质结构被布置在存储器栅极的相邻侧壁和控制栅极之间，并且布置在存储器栅极下方。 半导体结构的硬掩模布置在控制栅极上并且包括不对称轮廓。 不对称轮廓在远离记忆门的高度逐渐变细。 还提供了一种用于制造具有不对称轮廓的硬掩模的一对分裂栅极闪存单元器件的方法。

公开(公告)号：US09570454B2

公开(公告)日：2017-02-14

申请号：US14749970

申请日：2015-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu ,  Yu-Hsing Chang ,  Yuan-Tai Tseng

IPC: H01L27/115 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L27/11524 ,  H01L27/11534 ,  H01L29/1037 ,  H01L29/42328 ,  H01L29/7851

Abstract: The present disclosure relates to an integrated chip having a FinFET device and an embedded flash memory device, and a method of formation. In some embodiments, the integrated chip has a logic region and a memory region that is laterally separated from the logic region. The logic region has a first plurality of fins of semiconductor material protruding outward from a semiconductor substrate. A gate electrode is arranged over the first plurality of fins of semiconductor material. The memory region has a second plurality of fins of semiconductor material extending outward from the semiconductor substrate. An embedded flash memory cell is arranged onto the second plurality of fins of semiconductor material. The resulting integrated chip structure provides for good performance since it contains both a FinFET device and an embedded flash memory device.

Abstract translation: 本公开涉及具有FinFET器件和嵌入式闪存器件的集成芯片及其形成方法。 在一些实施例中，集成芯片具有与逻辑区域横向分离的逻辑区域和存储区域。 逻辑区域具有从半导体衬底向外突出的半导体材料的第一多个翅片。 栅电极设置在半导体材料的第一多个散热片上。 存储区域具有从半导体衬底向外延伸的第二多个半导体材料翅片。 嵌入式闪存单元被布置在半导体材料的第二多个鳍上。 所得到的集成芯片结构提供了良好的性能，因为它包含FinFET器件和嵌入式闪存器件。

公开(公告)号：US20170018562A1

公开(公告)日：2017-01-19

申请号：US15277137

申请日：2016-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure relates to a flash memory cell. In some embodiments, the flash memory cell has a control gate arranged over a substrate, and a select gate separated from the substrate by a gate dielectric layer. A charge trapping layer has a first portion disposed between the select gate and the control gate, and a second portion arranged under the control gate. A first control gate spacer is arranged on the second portion of the charge trapping layer. A second control gate spacer is arranged on the second portion of the charge trapping layer and is separated from the control gate by the first control gate spacer.

Abstract translation: 本公开涉及闪存单元。 在一些实施例中，快闪存储器单元具有布置在衬底上的控制栅极，以及通过栅极电介质层与衬底分离的选择栅极。 电荷捕获层具有设置在选择栅极和控制栅极之间的第一部分和布置在控制栅极下方的第二部分。 第一控制栅极间隔物布置在电荷俘获层的第二部分上。 第二控制栅极间隔物布置在电荷俘获层的第二部分上，并且通过第一控制栅极隔离物与控制栅极分离。