公开(公告)号：US20210098318A1

公开(公告)日：2021-04-01

申请号：US17121232

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Ding Wang ,  An-Jhih Su ,  Chien Ling Hwang ,  Jung Wei Cheng ,  Hsin-Yu Pan ,  Chen-Hua Yu

IPC: H01L23/04 ,  H01L23/42 ,  H01L23/367 ,  H01L23/00 ,  H01L23/10 ,  H01L21/56 ,  H01L25/065

Abstract: An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

公开(公告)号：US10192848B2

公开(公告)日：2019-01-29

申请号：US15712680

申请日：2017-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Jen Lin ,  Tsung-Ding Wang ,  Chien-Hsiun Lee ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/525

Abstract: In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.

公开(公告)号：US10074604B1

公开(公告)日：2018-09-11

申请号：US15499903

申请日：2017-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Cheng Hou ,  Chien-Hsun Lee ,  Hung-Jen Lin ,  Jung-Wei Cheng ,  Tsung-Ding Wang

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/31 ,  H01L23/12

CPC classification number: H01L23/12 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/19 ,  H01L2221/68345 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/18162

Abstract: A method of fabricating an integrated fan-out package is provided. The method includes the followings. An integrated circuit component is mounted on a carrier. An insulating encapsulation is formed on the carrier to encapsulate sidewalls of the integrated circuit component. A plurality of conductive pillars are formed on the integrated circuit component and a dielectric layer is formed to cover the integrated circuit component and the insulating encapsulation, wherein the plurality of conductive pillars penetrate through the dielectric layer and are electrically connected to the integrated circuit component. A redistribution circuit structure is formed on the dielectric layer and the plurality of conductive pillars, wherein the redistribution circuit structure is electrically connected to the integrated circuit component through the plurality of conductive pillars, and the redistribution circuit structure and the insulating encapsulation are spaced apart by the dielectric layer.

公开(公告)号：US20240310733A1

公开(公告)日：2024-09-19

申请号：US18334650

申请日：2023-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Chien-Hsun Lee ,  Tsung-Ding Wang ,  Hao-Cheng Hou

IPC: G03F7/20 ,  H01L21/48 ,  H01L23/538

CPC classification number: G03F7/2022 ,  H01L21/4857 ,  H01L23/5383 ,  H01L25/0652 ,  H01L25/0655

Abstract: A method includes forming a photoresist on a base structure, and performing a first light-exposure process on the photoresist using a first lithography mask. In the first light-exposure process, an inner portion of the photoresist is blocked from being exposed, and a peripheral portion of the photoresist is exposed. The peripheral portion encircles the inner portion. A second light-exposure process is performed on the photoresist using a second lithography mask. In the second light-exposure process, the inner portion of the photoresist is exposed, and the peripheral portion of the photoresist is blocked from being exposed. The photoresist is then developed.

公开(公告)号：US20240250067A1

公开(公告)日：2024-07-25

申请号：US18598250

申请日：2024-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Tsung-Ding Wang ,  Chien-Hsun Lee

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76879 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5389 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/08137 ,  H01L2224/08146 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/18162

Abstract: A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material is formed adjacent to the first die and the second die. A first redistribution layer is formed overlying the first molding material. A through via is formed over the first redistribution layer. A package component is on the first redistribution layer next to the copper pillar. The package component includes a second redistribution layer. The package component is positioned so that it overlies both the first die and the second die in part. A second molding material is formed adjacent to the package component and the first copper pillar. A third redistribution layer is formed overlying the second molding material. The second redistribution layer is placed on a substrate and bonded to the substrate.

公开(公告)号：US20240234302A1

公开(公告)日：2024-07-11

申请号：US18617530

申请日：2024-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shi Liu ,  Chien-Hsun Lee ,  Jiun Yi Wu ,  Hao-Cheng Hou ,  Hung-Jen Lin ,  Jung Wei Cheng ,  Tsung-Ding Wang ,  Yu-Min Liang ,  Li-Wei Chou

IPC: H01L23/522 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/5226 ,  H01L21/563 ,  H01L21/566 ,  H01L21/6835 ,  H01L21/76816 ,  H01L23/3157 ,  H01L23/49822 ,  H01L24/09 ,  H01L24/81 ,  H01L23/49816 ,  H01L24/13 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/02331 ,  H01L2224/13101 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.

公开(公告)号：US20240105631A1

公开(公告)日：2024-03-28

申请号：US18152558

申请日：2023-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jeng-An Wang ,  Sheng-Chi Lin ,  Hao-Cheng Hou ,  Tsung-Ding Wang ,  Chien-Hsun Lee

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68372 ,  H01L2224/214

Abstract: Embodiments provide a method of performing a carrier switch for a device wafer, attaching a second wafer and removing a first wafer. A buffer layer is deposited over the device wafer, buffer layer reducing the topography of the surface of the device wafer. After the carrier switch a film-on-wire layer is removed from the buffer layer and then the buffer layer is at least in part removed.

公开(公告)号：US11270921B2

公开(公告)日：2022-03-08

申请号：US16869596

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Cheng Hou ,  Chien-Hsun Lee ,  Chung-Shi Liu ,  Jung-Wei Cheng ,  Tsung-Ding Wang ,  Yi-Yang Lei

IPC: H01L23/29 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor package includes semiconductor dies, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The encapsulant encapsulates the semiconductor dies and is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the semiconductor dies. The high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer. The redistribution structure includes conductive patterns embedded in at least a pair of dielectric layers. The dielectric layers of the pair are made of a third material. The elastic modulus of the first material is higher than the elastic modulus of the third material. The elastic modulus of the second material is higher than the elastic modulus of the third material.

公开(公告)号：US20220020655A1

公开(公告)日：2022-01-20

申请号：US16933910

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Wei Cheng ,  Jiun-Yi Wu ,  Hsin-Yu Pan ,  Tsung-Ding Wang ,  Yu-Min Liang ,  Wei-Yu Chen

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/40

Abstract: A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern.

公开(公告)号：US20210384120A1

公开(公告)日：2021-12-09

申请号：US17408840

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shi Liu ,  Chien-Hsun Lee ,  Jiun Yi Wu ,  Hao-Cheng Hou ,  Hung-Jen Lin ,  Jung Wei Cheng ,  Tsung-Ding Wang ,  Yu-Min Liang ,  Li-Wei Chou

IPC: H01L23/522 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/768 ,  H01L21/683 ,  H01L23/498

Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.