公开(公告)号：US20100200432A1

公开(公告)日：2010-08-12

申请号：US12449732

申请日：2008-02-24

Applicant: Tatsuo Kamata ,  Takeshi Takagi

Inventor： Tatsuo Kamata ,  Takeshi Takagi

IPC: G01N27/26 ,  C01B21/08

CPC classification number: C12Q1/006 ,  C12Q1/28

Abstract: The present invention relates to a method, a reagent and an apparatus for determining a substrate concentration based on an amount of hydrogen peroxide generated from a substrate. In the present invention, a suppressing agent for suppressing a reaction between the hydrogen peroxide and an inhibitor is added. As the suppressing agent, an azide compound such as sodium azide or a nitrite compound such as sodium nitrite is used. In the invention, a supporting electrolyte, such as sodium chloride or potassium chloride may be further added.

Abstract translation: 本发明涉及一种基于从基底产生的过氧化氢量来确定底物浓度的方法，试剂和装置。 在本发明中，添加抑制过氧化氢与抑制剂的反应的抑制剂。 作为抑制剂，可以使用叠氮化钠等叠氮化合物，亚硝酸钠等亚硝酸酯化合物。 在本发明中，可以进一步添加氯化钠或氯化钾等担载电解质。

公开(公告)号：US20100148143A1

公开(公告)日：2010-06-17

申请号：US12600793

申请日：2008-05-16

Applicant: Satoru Fujii ,  Yoshihiko Kanzawa ,  Takeshi Takagi ,  Kazuhiko Shimakawa

Inventor： Satoru Fujii ,  Yoshihiko Kanzawa ,  Takeshi Takagi ,  Kazuhiko Shimakawa

IPC: H01L45/00 ,  H01L21/16

CPC classification number: H01L27/101 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/1625

Abstract: A nonvolatile semiconductor apparatus of the present invention comprises (103), a second electrode (105), and a resistance variable layer (104) disposed between the first electrode (103) and the second electrode (105), a resistance value of the resistance variable layer being switchable reversibly in response to an electric signal applied between the electrodes (103), (105), wherein the resistance variable layer (104) comprises an oxide containing tantalum and nitrogen.

Abstract translation: 本发明的非易失性半导体装置包括：（103），设置在第一电极（103）和第二电极（105）之间的第二电极（105）和电阻变化层（104），电阻值 可变层可响应施加在电极（103），（105）之间的电信号而可逆地切换，其中电阻变化层（104）包括含有钽和氮的氧化物。

公开(公告)号：US07729866B2

公开(公告)日：2010-06-01

申请号：US11666055

申请日：2005-10-25

Applicant: Koji Sugiyama ,  Takeshi Takagi

Inventor： Koji Sugiyama ,  Takeshi Takagi

IPC: G01N33/49 ,  G01N27/327 ,  C12Q1/26

CPC classification number: G01N27/3271

Abstract: The present invention relates to a method for measuring the concentration of a particular component in a blood sample containing blood cells based on a variable correlated with the concentration of the particular component. In the present invention, a concentration (S) in blood plasma obtained by removing blood cell components from the blood sample, a concentration (DI) in the blood sample computed by a differential method and a concentration (EP) in the blood sample computed by an equilibrium point method are expressed by a relational expression which is unrelated to the proportion of the blood cell components in the blood sample, and the concentration of the particular component is computed by using the relational expression.

Abstract translation: 本发明涉及基于与特定成分的浓度相关的变量来测定含有血细胞的血液样品中特定成分的浓度的方法。 在本发明中，通过从血液样品中除去血细胞成分而获得的血浆中的浓度（S），通过微分法计算的血液样品中的浓度（DI）和血液样品中的浓度（EP） 平衡点法由与血样中血细胞成分比例无关的关系表达式表示，特定成分的浓度用关系式计算。

公开(公告)号：US20090014710A1

公开(公告)日：2009-01-15

申请号：US12281034

申请日：2007-03-06

Applicant: Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

Inventor： Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

IPC: H01L45/00

CPC classification number: H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1658 ,  H01L45/1675

Abstract: A lower electrode layer 2, an upper electrode layer 4 formed above the lower electrode layer 2, and a metal oxide thin film layer 3 formed between the lower electrode layer 2 and the upper electrode layer 4 are provided. The metal oxide thin film layer 3 includes a first region 3a whose value of resistance increases or decreases by an electric pulse that is applied between the lower electrode layer 2 and the upper electrode layer 4 and a second region 3b arranged around the first region 3a and having a larger content of oxygen than the first region 3a, wherein the lower and upper electrode layers 2 and 4 and at least a part of the first region 3a are arranged so as to overlap as viewed from the direction of the thickness of the first region 3a.

Abstract translation: 设置下电极层2，形成在下电极层2上的上电极层4和形成在下电极层2和上电极层4之间的金属氧化物薄膜层3。 金属氧化物薄膜层3包括第一区域3a，其第一区域3a的电阻值通过施加在下电极层2和上电极层4之间的电脉冲和围绕第一区域3a布置的第二区域3b而增大或减小，以及 具有比第一区域3a更大的氧含量，其中下电极层2和上电极层4以及第一区域3a的至少一部分从第一区域的厚度方向观察而重叠 3a。

公开(公告)号：US07235830B2

公开(公告)日：2007-06-26

申请号：US11260197

申请日：2005-10-28

Applicant: Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Akira Inoue

Inventor： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Akira Inoue

IPC: H01L29/76

CPC classification number: H01L29/78696 ,  H01L21/76264 ,  H01L21/76281 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/78687 ,  Y10S438/933 ,  Y10S438/938

Abstract: The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3), the gate insulation film (10) and the gate electrode (11); wherein the first insulation film (13) overlies a part of the gate insulation film (10) surface. According to the semiconductor device, leakage current at the isolation edge can be suppressed and thus reliability can be improved.

Abstract translation: 本发明提供一种半导体器件，包括：半导体层（3）; 经由栅极绝缘膜（10）形成在所述半导体层（3）上的栅电极（11）; 以及形成在所述半导体层（3），所述栅极绝缘膜（10）和所述栅电极（11）的侧壁的一个或多个的第一绝缘膜（13）。 其中所述第一绝缘膜（13）覆盖所述栅极绝缘膜（10）表面的一部分。 根据半导体装置，可以抑制隔离边缘处的漏电流，从而可以提高可靠性。

公开(公告)号：US07170110B2

公开(公告)日：2007-01-30

申请号：US10983610

申请日：2004-11-09

Applicant: Akira Inoue ,  Takeshi Takagi ,  Yoshihiro Hara ,  Minoru Kubo

Inventor： Akira Inoue ,  Takeshi Takagi ,  Yoshihiro Hara ,  Minoru Kubo

IPC: H01L29/161 ,  H01L29/772

CPC classification number: H01L29/802 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/10873 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1222 ,  H01L28/55 ,  H01L29/1054 ,  H01L29/783 ,  H01L29/78687

Abstract: A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.

Abstract translation: 依次沉积硅衬底101上的氧化硅膜102，Pt膜103x，Ti膜104x和PZT膜105x。 将Si衬底101放置在室106中，使得PZT膜105x被EHF波108照射。 用EHF波照射局部加热电介质膜，例如PZT膜。 结果，可以改善例如电介质膜的泄漏特性，而不会对形成在Si衬底101上的器件产生不利影响。

公开(公告)号：US07133626B2

公开(公告)日：2006-11-07

申请号：US10902790

申请日：2004-08-02

Applicant: Miho Kaiga ,  Takeshi Takagi

Inventor： Miho Kaiga ,  Takeshi Takagi

IPC: G03G15/00 ,  H02J1/00

CPC classification number: G03G7/00 ,  G03G7/0053 ,  G03G21/1628 ,  G03G2215/00548 ,  G03G2221/1687

Abstract: An image forming apparatus includes an image forming portion for forming an image, an image reading portion for reading an image, displaceable with respect to the image forming portion, and an open/closable member that can be opened or closed with respect to a main body of the image forming portion and displaced toward the image reading portion, wherein the displacement of the open/closable member is effected in relation to the displacement of the image reading portion. In this manner the open/closable member can be opened or closed by a simple operation, without increasing the dimension of the image forming apparatus.

Abstract translation: 图像形成装置包括用于形成图像的图像形成部分，用于读取图像的图像读取部分，可相对于图像形成部分移位;以及打开/关闭部件，其可相对于主体打开或关闭 并且朝向图像读取部分移位，其中打开/关闭部件的位移相对于图像读取部分的位移进行。 以这种方式，可以通过简单的操作来打开或关闭打开/关闭构件，而不增加图像形成装置的尺寸。

公开(公告)号：US20050133834A1

公开(公告)日：2005-06-23

申请号：US10948747

申请日：2004-09-24

Applicant: Haruyuki Sorada ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

Inventor： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/66636 ,  H01L21/28202 ,  H01L29/1054 ,  H01L29/518 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842

Abstract: A semiconductor device of this invention includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a pair of source and drain electrodes respectively formed in regions of the semiconductor substrate situated on opposite sides of the gate electrode in a plan view; and a germanium-containing channel layer situated below the gate electrode to sandwich an gate insulator therebetween and intervening between the pair of source and drain electrodes, wherein a silicide layer forming at least a part of the source and drain electrodes has a lower germanium concentration than the channel layer.

Abstract translation: 本发明的半导体器件包括：半导体衬底; 形成在所述半导体衬底上的栅电极; 在平面图中分别形成在位于栅电极的相对侧的半导体衬底的区域中的一对源极和漏极; 以及位于栅极电极下方的含锗沟道层，以夹持栅极绝缘体，并且介于所述一对源极和漏极之间，其中形成所述源极和漏极的至少一部分的硅化物层的锗浓度低于 通道层。

公开(公告)号：US06876045B2

公开(公告)日：2005-04-05

申请号：US10626642

申请日：2003-07-25

Applicant: Takeshi Takagi

Inventor： Takeshi Takagi

IPC: H01L21/28 ,  H01L21/321 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/49 ,  H01L29/78 ,  H01L29/80 ,  H01L29/72

CPC classification number: H01L29/4983 ,  H01L21/2807 ,  H01L21/28105 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/32105 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/1054 ,  H01L29/7836 ,  H01L29/802

Abstract: This specification relates to a process for manufacturing a semiconductor device, comprising the steps of: forming a lower gate electrode film on a semiconductor substrate 10 via a gate insulating film 11; forming an upper gate electrode film on the lower gate electrode film, the upper gate electrode film being made of a material having a lower oxidation rate than that of the lower gate electrode film; forming a gate electrode 12 by patterning the upper gate electrode film and the lower gate electrode film, the gate electrode 12 comprising a lower gate electrode element 12a and an upper gate electrode element 12b; forming source/drain regions 15 by introducing an impurity into the semiconductor substrate 10; and forming oxide film sidewalls 13 by oxidizing the side faces of the lower gate electrode element 12a and the upper gate electrode element 12b, the thickness of the oxide film sidewalls 13 in the gate length direction being larger at the sides of the lower gate electrode element 12a than at the sides of the upper gate electrode element 12b.

Abstract translation: 本说明书涉及半导体器件的制造方法，其特征在于，包括以下步骤：通过栅极绝缘膜11在半导体衬底10上形成下部栅极电极膜; 在下栅电极膜上形成上栅极电极膜，上栅极电极膜由比下栅极电极膜氧化率低的材料制成; 通过图案化上栅极电极膜和下栅极电极膜形成栅电极12，栅电极12包括下栅电极元件12a和上栅极电极元件12b; 通过将杂质引入到半导体衬底10中来形成源/漏区15; 以及通过氧化下部栅极电极元件12a和上部栅极电极元件12b的侧面而形成氧化膜侧壁13，栅极长度方向上的氧化膜侧壁13的厚度在下部栅极电极元件的侧面较大 12a比在上栅极电极元件12b的侧面处。

公开(公告)号：US20050040436A1

公开(公告)日：2005-02-24

申请号：US10866093

申请日：2004-06-14

Applicant: Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

Inventor： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC: H01L21/8238 ,  H01L27/10

CPC classification number: H01L21/823807

Abstract: A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.

Abstract translation: 根据本发明的半导体集成电路制造方法包括：通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤，由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管 形成区域和一对第二装置形成区域。