公开(公告)号：US20070071894A1

公开(公告)日：2007-03-29

申请号：US11536472

申请日：2006-09-28

申请人： Fumitake Mieno

发明人： Fumitake Mieno

IPC分类号： C23C16/00

CPC分类号： C23C16/0227

摘要： A method for forming atomic layer deposition. The method includes placing a semiconductor substrate (e.g., wafer, LCD panel) including an upper surface in a chamber. The upper surface includes one or more carbon bearing species and a native oxide layer. The method includes introducing an oxidizing species into the chamber. The method includes treating the upper surface of the semiconductor substrate to remove the one or more carbon bearing species and form a particle film of silicon dioxide overlying the upper surface. The method includes introducing an inert gas into the chamber to purge the chamber of the oxidizing species and other species associated with the one or more carbon bearing species. A reducing species is introduced into the chamber to strip the particle film of silicon dioxide to create a substantially clean surface treated with hydrogen bearing species. The method includes performing another process (e.g., atomic layer deposition) on the substantially clean surface while the substrate is maintained in a vacuum environment. The substantially clean surface is substantially free from native oxide and carbon bearing particles.

摘要翻译： 一种形成原子层沉积的方法。 该方法包括将包括上表面的半导体衬底（例如，晶片，LCD面板）放置在腔室中。 上表面包括一个或多个碳承载物质和天然氧化物层。 该方法包括将氧化物质引入室中。 该方法包括处理半导体衬底的上表面以除去一种或多种含碳物质并形成覆盖在上表面上的二氧化硅的颗粒膜。 该方法包括将惰性气体引入室中以净化氧化物质的室和与一种或多种含碳物质相关联的其它物质。 将还原物质引入室中以剥离二氧化硅的颗粒膜以产生用含氢物质处理的基本上清洁的表面。 该方法包括在基板保持在真空环境中时在基本上清洁的表面上执行另一工艺（例如，原子层沉积）。 基本上干净的表面基本上不含有自然氧化物和碳的颗粒。

公开(公告)号：US5843829A

公开(公告)日：1998-12-01

申请号：US559813

申请日：1995-11-17

申请人： Masaki Kuramae ,  Fumitake Mieno

发明人： Masaki Kuramae ,  Fumitake Mieno

IPC分类号： C23C16/52 ,  H01L21/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L21/2022 ,  H01L28/84 ,  H01L28/87 ,  Y10S438/901

摘要： A method for fabricating a semiconductor device includes the steps of depositing an amorphous silicon layer on a substrate, and forming an oxidation film on a surface of the amorphous silicon layer by treating the surface of the amorphous silicon layer with an oxidation gas. The forming step occurs before crystallization of the amorphous silicon layer.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在衬底上沉积非晶硅层，并通过用氧化气体处理非晶硅层的表面，在非晶硅层的表面上形成氧化膜。 形成步骤在非晶硅层结晶之前发生。

公开(公告)号：US5609721A

公开(公告)日：1997-03-11

申请号：US367828

申请日：1995-01-03

申请人： Atsuhiro Tsukune ,  Kiyokatsu Suzuki ,  Katsuyoshi Matsuura ,  Fumitake Mieno ,  Hirokazu Yamanishi

发明人： Atsuhiro Tsukune ,  Kiyokatsu Suzuki ,  Katsuyoshi Matsuura ,  Fumitake Mieno ,  Hirokazu Yamanishi

IPC分类号： C23C16/44 ,  C23C16/455 ,  H01L21/00 ,  C23C16/00

CPC分类号： C23C16/45561 ,  C23C16/4405 ,  C23C16/4412 ,  C23C16/455 ,  H01L21/67028 ,  Y10S438/905

摘要： An apparatus and method for manufacturing a semiconductor device includes a reaction chamber adapted to exhaust gas therefrom, and a cleaning gas supplying system for introducing cleaning gas containing ClF.sub.3 into the reaction chamber, the system having a plurality of gas blowout holes formed in the flow direction of gas at least in the reaction chamber. The reaction chamber may be a tubular chamber, and the cleaning gas supplying system may be a tube extending from one end to the other end of the reaction chamber along the inner wall or the central axis of the reaction chamber, a plurality of through holes being formed in the side wall of the tube. Damages to the inner surface of the reaction chamber of the semiconductor device manufacturing apparatus can be suppressed and a film attached to the inner wall of the reaction chamber can be removed in a short time.

摘要翻译： 一种用于制造半导体器件的设备和方法，包括适于从其中排出的反应室和用于将含有ClF 3的清洁气体引入反应室的清洁气体供给系统，该系统具有沿流动方向形成的多个气体吹出孔 至少在反应室中。 反应室可以是管状室，并且清洁气体供应系统可以是沿着反应室的内壁或中心轴线从反应室的一端延伸到另一端的管，多个通孔是 形成在管的侧壁中。 能够抑制对半导体装置制造装置的反应室内表面的损伤，能够在短时间内除去附着于反应室内壁的膜。

公开(公告)号：US5233163A

公开(公告)日：1993-08-03

申请号：US725081

申请日：1991-07-03

申请人： Fumitake Mieno ,  Yuji Furumura ,  Atsuhiro Tsukune ,  Hiroshi Miyata

发明人： Fumitake Mieno ,  Yuji Furumura ,  Atsuhiro Tsukune ,  Hiroshi Miyata

IPC分类号： H01L21/205 ,  C23C16/46 ,  C30B29/06 ,  H01L21/00 ,  H01L21/324

CPC分类号： H01L21/67103

摘要： A heating apparatus for use in heating a substrate comprises an electric heater and a power supply part. The electric heater is made up of an approximately columnar body which is made of graphite, and this columnar body has a top with a flat surface part on which the substrate is placed and a pair of legs which extend downwardly from the flat surface part. The legs are defined by an opening in the columnar body. The power supplying part is coupled to the electric heater and supplies a voltage across the legs of the columnar body so that a current flows from one leg to the other, thereby generating heat at the flat surface part to heat the substrate.

摘要翻译： 用于加热基板的加热装置包括电加热器和电源部分。 电加热器由石墨制成的近似柱状的主体构成，并且该柱状体具有顶部，其具有放置基板的平坦表面部分和从平坦表面部分向下延伸的一对支腿。 腿由柱状体中的开口限定。 供电部分耦合到电加热器并且提供横跨柱状体的腿的电压，使得电流从一个腿流向另一个腿，由此在平坦表面部分处产生热量以加热衬底。

公开(公告)号：US5111266A

公开(公告)日：1992-05-05

申请号：US714367

申请日：1991-06-12

申请人： Yuji Furumura ,  Fumitake Mieno ,  Tsutomu Nakazawa ,  Takashi Eshita ,  Mamoru Maeda ,  Tsunenori Yamauchi

发明人： Yuji Furumura ,  Fumitake Mieno ,  Tsutomu Nakazawa ,  Takashi Eshita ,  Mamoru Maeda ,  Tsunenori Yamauchi

IPC分类号： H01L29/08 ,  H01L29/16 ,  H01L29/36 ,  H01L29/737

CPC分类号： H01L29/0817 ,  H01L29/1604 ,  H01L29/36 ,  H01L29/7375

摘要： A bipolar transistor includes a base region made of silicon crystal doped with a first impurity to a first level so as to establish a first carrier concentration in the base region and an emitter region made of silicon crystal doped with a second impurity to a second level substantially larger than the first level by a predetermined factor so as to establish a second carrier concentration in the emitter region, in which the second impurity exceeds the solubility limit of the second impurity in silicon crystal. The first and second levels are chosen in such a range that a difference in the carrier concentrations between the emitter region and the base region decreases substantially with increasing impurity level in the base region.

公开(公告)号：US08951871B2

公开(公告)日：2015-02-10

申请号：US13326322

申请日：2011-12-15

申请人： Fumitake Mieno

发明人： Fumitake Mieno

IPC分类号： H01L29/66 ,  H01L21/336 ,  H01L29/417 ,  H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/66545 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

摘要： This disclosure relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises: a patterned stacked structure formed on a semiconductor substrate, the stacked structure comprising a silicon-containing semiconductor layer overlaying the semiconductor substrate, a gate dielectric layer overlaying the silicon-containing semiconductor layer and a gate layer overlaying the gate dielectric layer; and a doped epitaxial semiconductor layer on opposing sides of the silicon-containing semiconductor layer forming raised source/drain extension regions. Optionally, the silicon-containing semiconductor layer may be used as a channel region. According to this disclosure, the source/drain extension regions can be advantageously made to have a shallow junction depth (or a small thickness) and a high doping concentration.

摘要翻译： 本公开涉及一种半导体器件及其制造方法。 所述半导体器件包括：形成在半导体衬底上的图案化叠层结构，所述堆叠结构包括覆盖所述半导体衬底的含硅半导体层，覆盖所述含硅半导体层的栅极电介质层和覆盖所述栅极介电层的栅极层 ; 以及在形成凸起的源极/漏极延伸区域的含硅半导体层的相对侧上的掺杂的外延半导体层。 可选地，含硅半导体层可以用作沟道区。 根据本公开，源极/漏极延伸区域可以有利地具有浅的结深度（或小的厚度）和高的掺杂浓度。

公开(公告)号：US08835213B2

公开(公告)日：2014-09-16

申请号：US13401819

申请日：2012-02-21

申请人： Fumitake Mieno

发明人： Fumitake Mieno

IPC分类号： H01L21/335 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01L21/3105

CPC分类号： H01L21/28194 ,  H01L21/02123 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/02307 ,  H01L21/3105 ,  H01L29/4983 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66553

摘要： A semiconductor device includes a substrate having an active region, a gate structure on the active region, and spacers formed on opposite sides of the gate structure. The gate structure includes a gate dielectric layer on the active region, a metal gate on the gate dielectric layer, and sidewalls on both side surfaces of the gate structure. Each of the sidewalls is interposed between the metal gate and one of the spacers. The sidewalls include a self-assembly material. The gate dielectric layer includes a high-K material. The spacers include silicon nitride. The gate structure also includes a buffer layer interposed between the metal gate and the gate dielectric layer.

摘要翻译： 半导体器件包括具有有源区的衬底，有源区上的栅极结构和形成在栅极结构的相对侧上的间隔物。 栅极结构包括有源区上的栅极电介质层，栅极电介质层上的金属栅极和栅极结构的两个侧表面上的侧壁。 每个侧壁插入在金属栅极和间隔件中的一个之间。 侧壁包括自组装材料。 栅介质层包括高K材料。 间隔物包括氮化硅。 栅极结构还包括介于金属栅极和栅极电介质层之间的缓冲层。

公开(公告)号：US08492213B2

公开(公告)日：2013-07-23

申请号：US13204319

申请日：2011-08-05

申请人： Fumitake Mieno

发明人： Fumitake Mieno

IPC分类号： H01L21/335 ,  H01L21/70

CPC分类号： H01L29/7833 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/7848 ,  H01L29/7849

摘要： The invention discloses a semiconductor device which comprises an NMOS transistor and a PMOS transistor formed on a substrate; and grid electrodes, source cathode doped areas, drain doped areas, and side walls formed on two sides of the grid electrodes are arranged on the NMOS transistor and the PMOS transistor respectively. The device is characterized in that the side walls on the two sides of the grid electrode of the NMOS transistor possess tensile stress, and the side walls on the two sides of the grid electrode of the PMOS transistor possess compressive stress. The stress gives the side walls a greater role in adjusting the stress applied to channels and the source/drain areas, with the carrier mobility further enhanced and the performance of the device improved.

摘要翻译： 本发明公开了一种半导体器件，其包括形成在衬底上的NMOS晶体管和PMOS晶体管; 并且分别在NMOS晶体管和PMOS晶体管上分别设置格栅电极，源极阴极掺杂区域，漏极掺杂区域和形成在栅电极两侧的侧壁。 该器件的特征在于，NMOS晶体管的栅电极的两侧的侧壁具有拉伸应力，并且PMOS晶体管的栅电极的两侧上的侧壁具有压应力。 应力使得侧壁在调节施加到通道和源极/漏极区域的应力方面发挥更大的作用，其中载流子迁移率进一步增强并且器件的性能得到改善。

公开(公告)号：US20130168746A1

公开(公告)日：2013-07-04

申请号：US13618004

申请日：2012-09-14

申请人： Fumitake Mieno

发明人： Fumitake Mieno

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： A semiconductor device manufacturing method includes providing a mask on a semiconductor member. The method further includes providing a dummy element to cover a portion of the mask that overlaps a first portion of the semiconductor member and to cover a second portion of the semiconductor member. The method further includes removing a third portion of the semiconductor member, which has not been covered by the mask or the dummy element. The method further includes providing a silicon compound that contacts the first portion of the semiconductor member. The method further includes removing the dummy element to expose and to remove the second portion of the semiconductor member. The method further includes forming a gate structure that overlaps the first portion of the semiconductor member. The first portion of the semiconductor member is used as a channel region and is supported by the silicon compound.

摘要翻译： 半导体器件制造方法包括在半导体部件上设置掩模。 该方法还包括提供虚拟元件以覆盖与半导体部件的第一部分重叠并覆盖半导体部件的第二部分的掩模的一部分。 该方法还包括去除未被掩模或虚拟元件覆盖的半导体部件的第三部分。 该方法还包括提供接触半导体部件的第一部分的硅化合物。 该方法还包括去除虚设元件以暴露并移除半导体部件的第二部分。 该方法还包括形成与半导体部件的第一部分重叠的栅极结构。 半导体部件的第一部分用作沟道区域并由硅化合物支撑。

公开(公告)号：US08409883B2

公开(公告)日：2013-04-02

申请号：US13157076

申请日：2011-06-09

申请人： Fumitake Mieno ,  Youfeng He

发明人： Fumitake Mieno ,  Youfeng He

IPC分类号： H01L21/00

CPC分类号： H01L45/06 ,  H01L27/15 ,  H01L27/24 ,  H01L45/1213 ,  H01L45/144

摘要： The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, peripheral shallow trench isolation (STI) units in the peripheral substrate, and MOS transistors on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, vertical LEDs on the on the N-type ion buried layer, storage shallow trench isolation (STI) units between the vertical LEDs, and phase change layers on the vertical LEDs and between the storage STI units. The storage STI units have thickness equal to thickness of the vertical LEDs. Each vertical LED comprises an N-type conductive region on the N-type ion buried layer, and a P-type conductive region on the N-type conductive region. The P-type conductive region contains SiGe. The peripheral STI units have thickness equal to thickness of the storage STI units. A top of P-type conductive region is flush with a top of the peripheral substrate. The P-type conductive region containing SiGe reduces drain current through the vertical LED and raises current efficiency of the vertical LED. The peripheral circuit region can work normally without adverse influence on performance of the phase change memory.

摘要翻译： 本发明提供一种相变存储器和形成相变存储器的方法。 相变存储器包括存储区域和外围电路区域。 外围电路区域具有周边基板，外围基板中的外围浅沟槽隔离（STI）单元，以及外围基板上的MOS晶体管和周边STI单元之间的MOS晶体管。 存储区具有存储基板，存储基板上的N型离子埋层，N型离子埋层上的垂直LED，垂直LED之间的存储浅沟槽隔离（STI）单元和相变层 在垂直LED和存储STI单元之间。 存储STI单元的厚度等于垂直LED的厚度。 每个垂直LED包括在N型离子掩埋层上的N型导电区域和N型导电区域上的P型导电区域。 P型导电区域含有SiGe。 外围STI单元的厚度等于存储STI单元的厚度。 P型导电区域的顶部与外围基板的顶部齐平。 含有SiGe的P型导电区域降低了通过垂直LED的漏极电流，提高了垂直LED的电流效率。 外围电路区域可以正常工作，而不会对相变存储器的性能产生不利影响。