公开(公告)号：US06876282B2

公开(公告)日：2005-04-05

申请号：US10150285

申请日：2002-05-17

Applicant: Panayotis Constantinou Andricacos ,  L. Paivikki Buchwalter ,  Hariklia Deligianni ,  Robert A. Groves ,  Christopher Jahnes ,  Jennifer L. Lund ,  Michael Meixner ,  David Earle Seeger ,  Timothy D. Sullivan ,  Ping-Chuan Wang

Inventor： Panayotis Constantinou Andricacos ,  L. Paivikki Buchwalter ,  Hariklia Deligianni ,  Robert A. Groves ,  Christopher Jahnes ,  Jennifer L. Lund ,  Michael Meixner ,  David Earle Seeger ,  Timothy D. Sullivan ,  Ping-Chuan Wang

IPC: H01H59/00 ,  H01H51/22

CPC classification number: H01H59/0009 ,  H01H2001/0078

Abstract: A microelectromechanical switch including: at least one pair of actuator electrodes; at least one input electrode and at least one output electrode for input and output, respectively, of a radio frequency signal; and a beam movable by an attraction between the at least one pair of actuator electrodes, the movable beam having at least a portion electrically connected to the at least one input electrode and to the at least one output electrode when moved by the attraction between the at least one pair of actuator electrodes to make an electrical connection between the at least one input and output electrodes; wherein the at least one pair of actuator electrodes are electrically isolated from each of the at least one input and output electrodes. The microelectromechanical switch can be configured in single or multiple-poles and/or single or multiple throws.

Abstract translation: 一种微机电开关，包括：至少一对致动器电极; 分别输入和输出射频信号的至少一个输入电极和至少一个输出电极; 以及可由所述至少一对致动器电极之间的吸引部移动的光束，所述可移动光束具有至少一部分电连接到所述至少一个输入电极，并且当所述至少一个输入电极在所述至少一个输入电极之间被所述吸引力移动时， 至少一对致动器电极，用于在所述至少一个输入和输出电极之间形成电连接; 其中所述至少一对致动器电极与所述至少一个输入和输出电极中的每一个电隔离。 微机电开关可以配置为单极或多极和/或单掷或多掷。

公开(公告)号：US06790744B2

公开(公告)日：2004-09-14

申请号：US10459974

申请日：2003-06-12

Applicant: Fen Chen ,  Timothy D. Sullivan

Inventor： Fen Chen ,  Timothy D. Sullivan

IPC: H01L2100

CPC classification number: H01L23/38 ,  H01L2924/0002 ,  Y10S257/93 ,  H01L2924/00

Abstract: A method and structure for a semiconductor structure that includes a substrate having at least one integrated circuit heat generating structure is disclosed. The invention has at least one integrated circuit cooling device on the substrate adjacent the heat generating structure. The cooling device is adapted to remove heat from the heat generating structure. The cooling device includes a cold region and a hot region. The cold region is positioned adjacent the heat generating structure. The cooling device has one of a silicon germanium super lattice structure. The cooling device also has a plurality of cooling devices that surround the heat generating structure. The cooling device includes a thermoelectric cooler.

公开(公告)号：US06512292B1

公开(公告)日：2003-01-28

申请号：US09660270

申请日：2000-09-12

Applicant: Douglas S. Armbrust ,  William F. Clark ,  William A. Klaasen ,  William T. Motsiff ,  Timothy D. Sullivan

Inventor： Douglas S. Armbrust ,  William F. Clark ,  William A. Klaasen ,  William T. Motsiff ,  Timothy D. Sullivan

IPC: H01L2312

CPC classification number: H01L23/5222 ,  H01L23/3677 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/10158 ,  H01L2924/00

Abstract: Semiconductor chip structures are provided with embedded thermal conductors for removing heat from one or more electrically conductive circuit members thereof, wherein the circuit members are formed on one or more dielectric layers above a substrate, each layer having a low dielectric constant and a low thermal conductivity. One or more cooling posts, for example, multiple thermally conductive plugs, are selectively disposed within the semiconductor chip structure adjacent to one or more electrically conductive members and thermally coupled thereto so that heat produced by the members is transferred into and through the cooling posts for forwarding to the substrate and/or to an upper surface of the semiconductor chip structure. The backside of the substrate has a thermal sink thermally coupled thereto and electrically isolated from the substrate. The thermal sink includes one or more thermally conductive via structures embedded within the substrate and aligned to thermally contact to the cooling posts disposed above the substrate.

Abstract translation: 半导体芯片结构设置有用于从一个或多个导电电路构件去除热量的嵌入式热导体，其中电路构件形成在衬底上方的一个或多个电介质层上，每层具有低介电常数和低热导率 。 一个或多个冷却柱，例如多个导热塞，被选择性地设置在半导体芯片结构内邻近一个或多个导电构件并与其热耦合，使得由构件产生的热量被传送到冷却柱中并通过冷却柱 转移到衬底和/或到半导体芯片结构的上表面。 衬底的背面具有热耦合到其上并与衬底电隔离的散热器。 散热器包括一个或多个热传导通孔结构，其嵌入衬底内并对准以与设置在衬底上方的冷却柱热接触。

公开(公告)号：US06417572B1

公开(公告)日：2002-07-09

申请号：US09354592

申请日：1999-07-16

Applicant: Dureseti Chidambarrao ,  Ronald G. Filippi ,  Robert Rosenberg ,  Thomas M. Shaw ,  Timothy D. Sullivan ,  Richard A. Wachnik

Inventor： Dureseti Chidambarrao ,  Ronald G. Filippi ,  Robert Rosenberg ,  Thomas M. Shaw ,  Timothy D. Sullivan ,  Richard A. Wachnik

IPC: H01L2348

CPC classification number: H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process for producing a multi-level semiconductor device having metal interconnections with insulating passivation layers and the product produced thereby. The product and process improve the resistance of the metallization interconnections to extrusion-short electromigration failures by preventing the insulating passivation layers from cracking. The product and process also reduce the level of resistance saturation or the maximum resistance shift caused by electromigration. By replacing wide-line metallization interconnection conducting lines surrounded by insulating passivation layers with two or more narrow, parallel conducting lines having aspect ratios less than or equal to unity with passivation layers located in between, the incidence of passivation cracking and extrusion-short failures is reduced. The process is especially suited for use in multi-level wiring structures in which the wiring levels have diffusion barriers between the wiring levels caused by redundant metallization layers, interlevel connections, or both.

Abstract translation: 一种制造具有绝缘钝化层的金属互连的多电平半导体器件的方法和由此产生的产品。 该产品和工艺通过防止绝缘钝化层开裂而改善金属化互连对挤出 - 短电迁移故障的阻力。 该产品和工艺也降低电阻饱和度或电迁移引起的最大电阻偏移。 通过用绝缘钝化层包围的宽线金属化互连导电线，其两个或更多个狭窄的平行导线，其纵横比小于或等于位于其间的钝化层的单位，钝化裂纹和挤出 - 短路故障的发生率是 减少 该方法特别适用于多层布线结构，其中布线层具有由冗余金属化层，层间连接或两者引起的布线水平之间的扩散障碍。

公开(公告)号：US06333557B1

公开(公告)日：2001-12-25

申请号：US09660271

申请日：2000-09-12

Applicant: Timothy D. Sullivan

Inventor： Timothy D. Sullivan

IPC: H01L2348

CPC classification number: H01L23/5329 ,  H01L23/3677 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor chip structures are provided with embedded thermal conductors for removing heat from one or more electrically conductive levels thereof, wherein the conductive levels are formed on a dielectric material having a low dielectric constant and low thermal conductivity. One or more cooling posts, e.g., multiple thermally conductive plugs are selectively disposed within the semiconductor chip structure adjacent to one or more electrically conductive levels and thermally coupled thereto so that heat produced by conductive lines within the wiring levels is transferred into and through the cooling posts for forwarding to a supporting substrate, which may have a back surface coupled to a cold plate, or to an upper surface of the semiconductor chip structure. The thermally conductive plugs of each cooling post have a second thermal conductivity, and the first thermal conductivity is less than the second thermal conductivity, for example, one third or less. As a specific example, the wiring levels may comprise copper, and the plurality of dielectric layers supporting the wiring levels may comprise a low k dielectric glass or nanofoam.

Abstract translation: 半导体芯片结构设置有用于从一个或多个导电水平移除热量的嵌入式热导体，其中导电水平形成在具有低介电常数和低热导率的电介质材料上。 一个或多个冷却柱，例如多个导热塞，选择性地设置在半导体芯片结构内，邻近一个或多个导电水平并与其热耦合，使得在布线层内的导线产生的热量被传递到冷却 用于转发到支撑衬底的柱，其可以具有连接到冷板的后表面或者到半导体芯片结构的上表面。 每个冷却柱的导热塞具有第二导热性，并且第一导热率小于第二导热率，例如小于或等于三分之一。 作为具体示例，布线水平可以包括铜，并且支撑布线水平的多个电介质层可以包括低k电介质玻璃或纳米电
波。

公开(公告)号：US06180506B2

公开(公告)日：2001-01-30

申请号：US09152836

申请日：1998-09-14

Applicant: Timothy D. Sullivan

Inventor： Timothy D. Sullivan

IPC: H01L214763

CPC classification number: H01L21/76858 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76877

Abstract: A multi-film damascene metal interconnect line for a semiconductor device and the method for manufacturing the interconnect line. The interconnect line has a redundant layer film included within the top surface of the interconnect line which reduces stress voiding and electromigration. The interconnect line is produced by depositing a redundant film part-way through the deposition of the bulk metal film and does not require additional polishing steps.

Abstract translation: 一种用于半导体器件的多层镶嵌金属互连线及其制造方法。 互连线具有包括在互连线的顶表面内的冗余层膜，其减少应力空隙和电迁移。 通过在块状金属膜的沉积中部分地沉积冗余膜并且不需要额外的抛光步骤来产生互连线。

公开(公告)号：US4184093A

公开(公告)日：1980-01-15

申请号：US922620

申请日：1978-07-07

Applicant: Timothy D. Sullivan

Inventor： Timothy D. Sullivan

IPC: B06B1/06 ,  H04R17/02 ,  H01L41/10

CPC classification number: H04R17/025 ,  B06B1/0688 ,  Y10S310/80

Abstract: A transducer, suitable for sensing acoustic signals underwater, includes aiezoelectric polymer film. The device comprises a rectangular sandwich arrangement with a plastic frame in the center having plastic plates connected on either side and a piezoelectric polymer film on the outside of each plastic plate. The film is arranged so that the most active direction of the polymer lies in the transverse plate direction. Electric wires are connected to opposing surfaces of each piezoelectric polymer film. When the sandwich arrangement is complete an air cavity that is compliant to the stiffness of the plates is created in the center within the plastic frame.

Abstract translation: 适用于水下感测声学信号的传感器包括压电聚合物膜。 该装置包括矩形夹层结构，其中心具有塑料框架，其中塑料板在两侧连接，压电聚合物膜位于每个塑料板的外侧。 该膜被布置成使得聚合物的最活跃的方向位于横向板方向上。 电线连接到每个压电聚合物膜的相对表面。 当三明治布置完成时，在塑料框架的中心产生符合板的刚度的空气腔。

公开(公告)号：US08592947B2

公开(公告)日：2013-11-26

申请号：US12962722

申请日：2010-12-08

Applicant: Joseph M. Lukaitis ,  Deborah M. Massey ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Kimball M. Watson

Inventor： Joseph M. Lukaitis ,  Deborah M. Massey ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC: H01L23/36

CPC classification number: H01L28/20 ,  H01L23/3677 ,  H01L23/5228 ,  H01L27/0211 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.

Abstract translation: 制造该结构的结构和方法包括：半导体衬底，其具有限定水平方向的顶表面和从最接近半导体衬底的顶表面的最底层到距离顶表面最远的最高水平层叠的多个互连层。 每个互连层包括在垂直于水平方向的垂直方向上彼此物理连接的垂直金属导体。 最底层的垂直导体物理地连接到衬底的顶表面，垂直导体形成连接到半导体衬底的散热片。 一个电阻器被包含在最上层的上方的层中。 垂直导体在电阻器的向下垂直电阻器占位面下对准，并且每个互连级别还包括位于水平方向上并且连接到垂直导体的水平金属导体。

公开(公告)号：US08541864B2

公开(公告)日：2013-09-24

申请号：US13588218

申请日：2012-08-17

Applicant: Joseph M. Lukaitis ,  Jed H. Rankin ,  Robert R. Robison ,  Dustin K. Slisher ,  Timothy D. Sullivan

Inventor： Joseph M. Lukaitis ,  Jed H. Rankin ,  Robert R. Robison ,  Dustin K. Slisher ,  Timothy D. Sullivan

IPC: H01L29/02

CPC classification number: H01L27/1203 ,  H01L28/20

Abstract: A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate, and forming at least one dielectric layer over the resistor. The method also includes forming a substrate contact through the at least one dielectric layer, through the resistor, through the insulator layer, and into the substrate. The substrate contact comprises a high thermal conductivity material.

Abstract translation: 形成半导体结构的方法包括在衬底上的绝缘体层上形成电阻器，并且在电阻器上方形成至少一个电介质层。 所述方法还包括通过所述至少一个电介质层，通过所述电阻器，穿过所述绝缘体层，并进入所述衬底形成衬底接触。 衬底接触包括高导热性材料。

公开(公告)号：US20130234315A1

公开(公告)日：2013-09-12

申请号：US13414877

申请日：2012-03-08

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L22/30 ,  H01L22/12 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05584 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13028 ,  H01L2224/13111 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/3841 ,  H01L2224/11 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: Structures and methods for detecting solder wetting of pedestal sidewalls. The structure includes a semiconductor wafer having an array of integrated circuit chips, each of the integrated circuit chips having an array of chip pedestals having respective chip solder columns on top of the chip pedestals, the pedestals spaced apart a first distance in a first direction and a spaced apart second distance in second direction perpendicular to the first direction; and at least one monitor structure disposed in different regions of the wafer from the integrated circuit chips, the monitor structure comprising at least a first pedestal and a first solder column on a top surface of the first pedestal and a second pedestal and a second solder column on a top surface of the second pedestal, the first and the second pedestals spaced apart a third distance, the third distance less than the first and the second distances.

Abstract translation: 用于检测基座侧壁焊料润湿的结构和方法。 该结构包括具有集成电路芯片阵列的半导体晶片，每个集成电路芯片具有芯片基座阵列，其具有位于芯片基座顶部的相应的芯片焊料柱，基座沿第一方向隔开第一距离;以及 在垂直于第一方向的第二方向上间隔开的第二距离; 以及设置在所述晶片与所述集成电路芯片的不同区域中的至少一个监视器结构，所述监视器结构至少包括在所述第一基座的顶表面上的第一基座和第一焊料柱，以及第二基座和第二焊接柱 在第二基座的顶表面上，第一和第二基座间隔第三距离，第三距离小于第一和第二距离。