公开(公告)号：US07335550B2

公开(公告)日：2008-02-26

申请号：US11641138

申请日：2006-12-19

申请人： Jae-hyoung Choi ,  Wan-don Kim ,  Cha-young Yoo ,  Suk-jin Chung

发明人： Jae-hyoung Choi ,  Wan-don Kim ,  Cha-young Yoo ,  Suk-jin Chung

IPC分类号： H01L21/8234

CPC分类号： H01L28/65 ,  H01L28/40

摘要： Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer and the dielectric layer can be removed, and a thermal process can be performed on the second conductive layer and the dielectric layer. The thermal process can reduce interface stress between the second conductive layer and the dielectric layer and/or cure the dielectric layer. In addition, the dielectric layer may be maintained in an amorphous state during and after the thermal process.

摘要翻译： 用于制造半导体存储器件的方法可以包括在半导体衬底上形成用于第一电极的第一导电层，在第一导电层上形成电介质层，以及在电介质层上形成用于第二电极的第二导电层。 可以去除第二导电层和电介质层的部分，并且可以在第二导电层和电介质层上进行热处理。 热处理可以减少第二导电层和电介质层之间的界面应力和/或固化电介质层。 此外，在热处理期间和之后，电介质层可以保持在非晶状态。

公开(公告)号：US06580111B2

公开(公告)日：2003-06-17

申请号：US09863679

申请日：2001-05-23

申请人： Wan-don Kim ,  Jin-won Kim ,  Seok-jun Won ,  Cha-young Yoo

发明人： Wan-don Kim ,  Jin-won Kim ,  Seok-jun Won ,  Cha-young Yoo

IPC分类号： H01L27108

CPC分类号： H01L21/02183 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/31604 ,  H01L28/91

摘要： A metal-insulator-metal (MIM) capacitor of a semiconductor device, and a manufacturing method thereof, includes a lower electrode formed of a refractory metal or a conductive compound including the refractory metal, a dielectric film formed of a high dielectric material, and an upper electrode formed of a platinum-family metal or a platinum-family metal oxide. Accordingly, the MIM capacitor satisfies the criteria of step coverage, electrical characteristics and manufacturing costs, as compared to a conventional MIM capacitor in which the upper and lower electrodes are formed of the same material such as a platinum-family metal, a refractory metal or a conductive compound including the refractory metal. The capacitor is especially suitable for mass production in semiconductor fabrication processes.

摘要翻译： 半导体器件的金属 - 绝缘体 - 金属（MIM）电容器及其制造方法包括由难熔金属形成的下电极或包含难熔金属的导电化合物，由高电介质材料形成的电介质膜，以及 由铂族金属或铂族金属氧化物形成的上电极。 因此，与常规的MIM电容器相比，MIM电容器满足阶梯覆盖，电特性和制造成本的标准，其中上电极和下电极由相同的材料形成，例如铂族金属，难熔金属或 包括难熔金属的导电化合物。 电容器特别适用于半导体制造工艺中的批量生产。

公开(公告)号：US07091102B2

公开(公告)日：2006-08-15

申请号：US10742727

申请日：2003-12-19

申请人： Han-jin Lim ,  Kwang-hee Lee ,  Suk-jin Chung ,  Cha-young Yoo ,  Wan-don Kim ,  Jin-il Lee

发明人： Han-jin Lim ,  Kwang-hee Lee ,  Suk-jin Chung ,  Cha-young Yoo ,  Wan-don Kim ,  Jin-il Lee

IPC分类号： H01L21/20 ,  H01L27/108

CPC分类号： H01L28/40 ,  H01L21/3141 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/57 ,  H01L28/65 ,  H01L28/91 ,  H01L28/92

摘要： An integrated circuit device is formed by providing a substrate and forming a capacitor on the substrate. The capacitor includes a lower electrode disposed on the substrate, a dielectric layer on the lower electrode, and an upper electrode on the dielectric. A hydrogen barrier insulation layer is formed on the upper electrode and a hydrogen barrier spacer is formed on a sidewall of the capacitor.

摘要翻译： 通过提供衬底并在衬底上形成电容器形成集成电路器件。 电容器包括设置在基板上的下电极，下电极上的电介质层和电介质上的上电极。 在上电极上形成氢阻隔绝缘层，在电容器的侧壁上形成氢阻挡隔离层。

公开(公告)号：US20060138511A1

公开(公告)日：2006-06-29

申请号：US11360070

申请日：2006-02-23

申请人： Suk-jin Chung ,  Wan-don Kim ,  Cha-young Yoo ,  Kwang-hee Lee ,  Han-jin Lim ,  Jin-il Lee

发明人： Suk-jin Chung ,  Wan-don Kim ,  Cha-young Yoo ,  Kwang-hee Lee ,  Han-jin Lim ,  Jin-il Lee

IPC分类号： H01L29/94

CPC分类号： H01L28/65 ,  H01L27/10852 ,  H01L28/91

摘要： Capacitors include an integrated circuit (semiconductor) substrate and an interlayer dielectric disposed on the integrated circuit substrate and including a metal plug therein. A lower electrode is disposed on the interlayer dielectric and contacting the metal plug. The lower electrode includes a cavity therein and a buried layer in the cavity. The buried layer is an oxygen absorbing material. A dielectric layer disposed on the lower electrode and an upper electrode is disposed on the dielectric layer. The lower electrode may be a noble metal layer. The buried layer may fill in the cavity and may not contain oxygen (O2) when initially formed.

摘要翻译： 电容器包括集成电路（半导体）基板和布置在集成电路基板上并且在其中包括金属插塞的层间电介质。 下部电极设置在层间电介质上并接触金属插塞。 下电极在其中包括空腔，并且在腔中包括掩埋层。 掩埋层是吸氧材料。 设置在下电极上的电介质层和上电极设置在电介质层上。 下电极可以是贵金属层。 当初始形成时，掩埋层可以填充空腔并且可以不含有氧（O 2 2 N）。

公开(公告)号：US20160315164A1

公开(公告)日：2016-10-27

申请号：US15048797

申请日：2016-02-19

申请人： Hyeok-jun Son ,  Wan-don Kim ,  Hoon-joo Na ,  Sang-jin Hyun ,  Yoon-tae Hwang ,  Jae-yeol Song

发明人： Hyeok-jun Son ,  Wan-don Kim ,  Hoon-joo Na ,  Sang-jin Hyun ,  Yoon-tae Hwang ,  Jae-yeol Song

IPC分类号： H01L29/49 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L29/4958 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7851

摘要： Semiconductor devices are provided. A semiconductor device includes an insulating layer. The semiconductor device includes a rare earth element supply layer on the insulating layer. Moreover, the semiconductor device includes a metal layer that is on the rare earth element supply layer. The rare earth element supply layer is between the insulating layer and the metal layer. Methods of forming semiconductor devices are also provided.

摘要翻译： 提供半导体器件。 半导体器件包括绝缘层。 半导体器件包括在绝缘层上的稀土元素供给层。 此外，半导体器件包括在稀土元素供给层上的金属层。 稀土元素供给层位于绝缘层与金属层之间。 还提供了形成半导体器件的方法。

公开(公告)号：US06893501B2

公开(公告)日：2005-05-17

申请号：US10320407

申请日：2002-12-17

申请人： Ki-chul Kim ,  Sung-tae Kim ,  Young-sun Kim ,  Jeong-hee Chung ,  Wan-don Kim ,  Yun-jung Lee ,  Han-mei Choi

发明人： Ki-chul Kim ,  Sung-tae Kim ,  Young-sun Kim ,  Jeong-hee Chung ,  Wan-don Kim ,  Yun-jung Lee ,  Han-mei Choi

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/316 ,  H01L21/8242 ,  C30B25/04

CPC分类号： H01L28/57 ,  H01L21/02183 ,  H01L21/02271 ,  H01L21/02356 ,  H01L21/31637 ,  H01L27/1085 ,  H01L28/65

摘要： A method for manufacturing a capping layer covering a capacitor of a semiconductor memory device, preferably a metal-insulator-metal (MIM) capacitor, wherein the method includes forming a capacitor having a lower electrode, a dielectric layer and an upper electrode on a semiconductor substrate, forming a capping layer on the capacitor, and crystallizing the dielectric layer. Here, forming the capping layer includes stabilizing for deposition of the capping layer without providing oxygen gas, depositing the capping layer by providing a reaction source for the capping layer; and purging an inside of a reactor for forming the capping layer.

摘要翻译： 一种覆盖半导体存储器件的电容器，优选金属 - 绝缘体 - 金属（MIM）电容器的覆盖层的方法，其中所述方法包括在半导体上形成具有下电极，电介质层和上电极的电容器 衬底，在电容器上形成覆盖层，并使介电层结晶。 这里，形成覆盖层包括在不提供氧气的情况下沉积封盖层的稳定性，通过为封盖层提供反应源沉积覆盖层; 并且清洗用于形成覆盖层的反应器的内部。

公开(公告)号：US08859383B2

公开(公告)日：2014-10-14

申请号：US13424825

申请日：2012-03-20

申请人： Youn-soo Kim ,  Jae-hyoung Choi ,  Kyu-ho Cho ,  Wan-don Kim ,  Jae-soon Lim ,  Sang-yeol Kang

发明人： Youn-soo Kim ,  Jae-hyoung Choi ,  Kyu-ho Cho ,  Wan-don Kim ,  Jae-soon Lim ,  Sang-yeol Kang

IPC分类号： H01L21/20 ,  H01L49/02 ,  H01L21/02 ,  H01L21/316 ,  H01L21/318 ,  H01L27/108

CPC分类号： H01L28/56 ,  H01L21/02189 ,  H01L21/022 ,  H01L21/02244 ,  H01L21/02247 ,  H01L21/31683 ,  H01L21/318 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/75

摘要： A semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, the semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film.

摘要翻译： 一种半导体器件，具有具有改善的电特性和相关方法的电介质层，所述半导体器件包括顺序地设置在半导体衬底上的下金属层，电介质层和上金属层，以及设置在电介质层之间的插入层 下金属层和上金属层中的至少一个，其中电介质层包括金属氧化物膜，并且插入层包括金属材料膜。

公开(公告)号：US09793368B2

公开(公告)日：2017-10-17

申请号：US15048797

申请日：2016-02-19

申请人： Hyeok-jun Son ,  Wan-don Kim ,  Hoon-joo Na ,  Sang-jin Hyun ,  Yoon-tae Hwang ,  Jae-yeol Song

发明人： Hyeok-jun Son ,  Wan-don Kim ,  Hoon-joo Na ,  Sang-jin Hyun ,  Yoon-tae Hwang ,  Jae-yeol Song

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L29/51

CPC分类号： H01L29/4958 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7851

摘要： Semiconductor devices are provided. A semiconductor device includes an insulating layer. The semiconductor device includes a rare earth element supply layer on the insulating layer. Moreover, the semiconductor device includes a metal layer that is on the rare earth element supply layer. The rare earth element supply layer is between the insulating layer and the metal layer. Methods of forming semiconductor devices are also provided.

公开(公告)号：US20160308012A1

公开(公告)日：2016-10-20

申请号：US15059673

申请日：2016-03-03

申请人： Jae-yeol Song ,  Wan-don Kim ,  Sang-jin Hyun ,  Jin-wook Lee ,  Kee-sang Kwon ,  Ki-hyung Ko ,  Sung-woo Myung

发明人： Jae-yeol Song ,  Wan-don Kim ,  Sang-jin Hyun ,  Jin-wook Lee ,  Kee-sang Kwon ,  Ki-hyung Ko ,  Sung-woo Myung

IPC分类号： H01L29/423 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L29/42376 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/823456 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： In a semiconductor device including a gate line having a relatively narrow width and a relatively smaller pitch and a method of manufacturing the semiconductor device, the semiconductor device includes a substrate having a fin-type active region, a gate insulating layer that covers an upper surface and sides of the fin-type active region, and a gate line that extends and intersects the fin-type active region while covering the upper surface and the both sides of the fin-type active region, the gate line being on the gate insulating layer, wherein a central portion of an upper surface of the gate line in a cross-section perpendicular to an extending direction of the gate line has a concave shape.

摘要翻译： 在包括具有相对窄的宽度和相对较小的间距的栅极线的半导体器件和制造该半导体器件的方法中，所述半导体器件包括具有鳍式有源区的衬底，覆盖上表面的栅极绝缘层 翅片型有源区的侧面以及覆盖翅片型有源区的上表面和两侧的鳍型有源区延伸并相交的栅极线，栅极线位于栅极绝缘层上 其特征在于，所述栅极线的上表面的与所述栅极线的延伸方向垂直的截面的中心部分具有凹形。

公开(公告)号：US06500763B2

公开(公告)日：2002-12-31

申请号：US09735901

申请日：2000-12-14

申请人： Jin-won Kim ,  Sang-don Nam ,  Wan-don Kim ,  Kab-jin Nam

发明人： Jin-won Kim ,  Sang-don Nam ,  Wan-don Kim ,  Kab-jin Nam

IPC分类号： H01L21302

CPC分类号： H01L28/91 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31122

摘要： A method for manufacturing an electrode of a capacitor used in a semiconductor device, wherein a support insulating layer, an etch stop layer including a tantalum oxide layer, and a mold sacrificial insulating layer are sequentially formed on a semiconductor substrate. The mold sacrificial insulating layer, the etch stop layer and the support insulating layer are sequentially patterned to form a three-dimensional mold for a storage node. A storage node layer is formed to cover the inner surface of the mold. Next, storage nodes for capacitors are formed by dividing the storage node layer. The residual mold sacrificial insulating layer is removed by selectively wet etching, using the tantalum oxide layer as an etch stopper.

摘要翻译： 在半导体器件中制造用于电容器的电极的方法，其中在半导体衬底上依次形成支撑绝缘层，包括氧化钽层的蚀刻停止层和模具牺牲绝缘层。 模具牺牲绝缘层，蚀刻停止层和支撑绝缘层被顺序地图案化以形成用于存储节点的三维模具。 形成存储节点层以覆盖模具的内表面。 接下来，通过划分存储节点层来形成用于电容器的存储节点。 通过使用氧化钽层作为蚀刻停止器，通过选择性湿法蚀刻除去残余模具牺牲绝缘层。