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    Method controlling read sequence of nonvolatile memory device and memory system performing same
    22.
    发明授权
    Method controlling read sequence of nonvolatile memory device and memory system performing same 有权
    方法控制非易失性存储器件的读取顺序和执行相同的存储器系统

    公开(公告)号：US09431123B2

    公开(公告)日：2016-08-30

    申请号：US14457424

    申请日：2014-08-12

    申请人： Kyung-Ryun Kim

    发明人： Kyung-Ryun Kim

    IPC分类号： G11C16/32 ,  G11C16/26 ,  G11C29/02 ,  G11C16/00

    CPC分类号： G11C16/32 ,  G11C16/00 ,  G11C16/26 ,  G11C29/023 ,  G11C29/028

    摘要： To control a read sequence of a nonvolatile memory device, a plurality of read sequences are set and the read sequences respectively correspond to operating conditions different from each other. The read sequences are performed selectively based on sequence selection rates respectively corresponding to the read sequences. Read latencies of the respective read sequences are monitored and the sequence selection rates are adjusted based on monitoring results of the read latencies.

    摘要翻译： 为了控制非易失性存储器件的读取序列，设置多个读取序列，读取序列分别对应于彼此不同的操作条件。 基于分别对应于读取序列的序列选择速率来选择性地执行读取序列。 监视各个读取序列的读取延迟，并且基于读取延迟的监视结果来调整序列选择速率。

    Methods, systems, and computer readable media for early detection of potential flash failures using an adaptive system level algorithm based on flash program verify
    25.
    发明授权
    Methods, systems, and computer readable media for early detection of potential flash failures using an adaptive system level algorithm based on flash program verify 有权
    使用基于闪存程序验证的自适应系统级算法来早期检测潜在闪存故障的方法，系统和计算机可读介质

    公开(公告)号：US09349476B2

    公开(公告)日：2016-05-24

    申请号：US13773570

    申请日：2013-02-21

    申请人： SanDisk Technologies Inc.

    发明人： Assaf Pe'er

    IPC分类号： G11C16/34 ,  G11C29/02 ,  G11C11/56 ,  G11C16/00 ,  G11C29/04

    CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/00 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2211/5621

    摘要： Methods, systems, and computer readable media for early detection of potential flash failures using an adaptive system level algorithm based on NAND program verify are disclosed. According to one aspect, a method for early detection of potential flash failures using an adaptive system level algorithm based on NAND program verify includes performing a program verify operation after a write to a non-volatile memory, where the program verify mechanism reports a pass or fail based on an existing measurement threshold value, and dynamically adjusting the measurement threshold value used by subsequent program verify operations based on the results of previous program verify operations.

    摘要翻译： 公开了使用基于NAND程序验证的自适应系统级算法来早期检测潜在闪存故障的方法，系统和计算机可读介质。 根据一个方面，一种使用基于NAND程序验证的自适应系统级算法来早期检测潜在闪存故障的方法包括在写入非易失性存储器之后执行程序验证操作，其中程序验证机制报告通过或 基于现有测量阈值失效，并且基于先前的程序验证操作的结果动态地调整后续程序验证操作所使用的测量阈值。

    Semiconductor storage device having nonvolatile semiconductor memory
    26.
    发明授权
    Semiconductor storage device having nonvolatile semiconductor memory 有权
    具有非易失性半导体存储器的半导体存储装置

    公开(公告)号：US09299455B2

    公开(公告)日：2016-03-29

    申请号：US13500057

    申请日：2012-03-06

    申请人： Akifumi Suzuki ,  Takashi Tsunehiro

    发明人： Akifumi Suzuki ,  Takashi Tsunehiro

    IPC分类号： G11C29/02 ,  G11C16/34 ,  G11C16/00

    CPC分类号： G06F3/0616 ,  G06F3/0629 ,  G06F3/0679 ,  G11C16/00 ,  G11C16/3431 ,  G11C16/3495 ,  G11C29/021 ,  G11C29/028

    摘要： A semiconductor storage device has a nonvolatile semiconductor memory comprised from multiple storage areas, and a controller, which is coupled to the nonvolatile semiconductor memory. The controller (A) identifies a storage area state, which is the state of a storage area, (B) decides, based on the storage area state identified in the (A), a read parameter, which is a parameter for use when reading data from a storage area with respect to a storage area of this storage area state, and (C) uses the read parameter decided in the (B) with respect to a read-target storage area and reads data from this read-target storage area.

    摘要翻译： 半导体存储装置具有由多个存储区域构成的非易失性半导体存储器和耦合到非易失性半导体存储器的控制器。 控制器（A）识别作为存储区域的状态的存储区域状态，（B）基于（A）中识别的存储区域状态来决定作为读取时使用的参数的读取参数 来自相对于该存储区域状态的存储区域的存储区域的数据，（C）使用关于读取目标存储区域的（B）中所决定的读取参数，并从该读取对象存储区域读取数据 。

    DETERMINING BIAS INFORMATION FOR OFFSETTING OPERATING VARIATIONS IN MEMORY CELLS
    27.
    发明申请
    DETERMINING BIAS INFORMATION FOR OFFSETTING OPERATING VARIATIONS IN MEMORY CELLS 有权
    确定存储器中操作变量的偏移信息

    公开(公告)号：US20160077753A1

    公开(公告)日：2016-03-17

    申请号：US14948229

    申请日：2015-11-20

    申请人： HGST Technologies Santa Ana, Inc.

    发明人： Aldo G. COMETTI ,  Pablo Alejandro ZIPEROVICH

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0619 ,  G06F3/0629 ,  G06F3/0679 ,  G06F12/0246 ,  G11C11/1675 ,  G11C11/413 ,  G11C11/5628 ,  G11C16/00 ,  G11C16/0483 ,  G11C16/3454

    摘要： Disclosed is an apparatus and method for determining memory cell bias information for use in memory operations. One or more memory die are selected from a group of memory die, and one or more memory blocks selected from the selected one or more memory die. A group of cells within the selected memory blocks are programmed and cycled. Bias values are generated based on comparing one or more program levels associated with respective wordlines with predetermined programming levels. The bias values are stored lookup table that is configured to be accessible at runtime by a memory controller for retrieval of the bias value during a memory operation.

    摘要翻译： 公开了一种用于确定存储器操作中使用的存储单元偏移信息的装置和方法。 从一组存储器管芯选择一个或多个存储器管芯，以及从所选择的一个或多个存储器管芯中选择的一个或多个存储器块。 所选存储块内的一组单元被编程和循环。 基于将与相应字线相关联的一个或多个程序级与预定编程级别进行比较来生成偏置值。 偏置值是存储查找表，其被配置为在运行时由存储器控制器访问以在存储器操作期间检索偏置值。

    Triggering a Process to Reduce Declared Capacity of a Storage Device in a Multi-Storage-Device Storage System
    28.
    发明申请
    Triggering a Process to Reduce Declared Capacity of a Storage Device in a Multi-Storage-Device Storage System 有权
    触发在多存储设备存储系统中减少存储设备的容量的过程

    公开(公告)号：US20160062665A1

    公开(公告)日：2016-03-03

    申请号：US14621237

    申请日：2015-02-12

    申请人： SanDisk Technologies Inc.

    发明人： Allen Samuels ,  Warren Fritz Kruger ,  Linh Tien Truong

    IPC分类号： G06F3/06 ,  G06F12/02

    CPC分类号： G06F3/0608 ,  G06F3/0616 ,  G06F3/0629 ,  G06F3/0661 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7204 ,  G06F2212/7205 ,  G06F2212/7211 ,  G11C16/00

    摘要： Systems, methods and/or devices are used to enable triggering a process to reduce declared capacity of a storage device in a multi-storage-device storage system. In one aspect, the method includes: (1) obtaining, for each storage device of a plurality of storage devices of the storage system, one or more metrics of the storage device, the storage device including non-volatile memory, (2) detecting a trigger condition for reducing declared capacity of the non-volatile memory of a respective storage device of the plurality of storage devices, the trigger condition detected in accordance with the one or more metrics of one or more storage devices, and (3) enabling an amelioration process associated with the detected trigger condition, the amelioration process to reduce declared capacity of the non-volatile memory of the respective storage device. In some embodiments, the respective storage device includes one or more flash memory devices.

    摘要翻译： 使用系统，方法和/或设备来触发过程以减少多存储设备存储系统中存储设备的声明容量。 一方面，该方法包括：（1）为存储系统的多个存储装置的各个存储装置获得存储装置的一个或多个度量值，存储装置包括非易失性存储器，（2）检测 用于减少所述多个存储装置的相应存储装置的所述非易失性存储器的声明容量的触发条件，根据一个或多个存储装置的一个或多个度量检测到的所述触发条件，以及（3）使能 与检测到的触发条件相关联的改善处理，减少相应存储设备的非易失性存储器的声明容量的改进处理。 在一些实施例中，相应的存储设备包括一个或多个闪存设备。

    Semiconductor device and method for manufacturing semiconductor device
    29.
    发明授权
    Semiconductor device and method for manufacturing semiconductor device 有权
    半导体装置及半导体装置的制造方法

    公开(公告)号：US09269822B2

    公开(公告)日：2016-02-23

    申请号：US14479623

    申请日：2014-09-08

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Yoshitaka Yamamoto ,  Tetsuhiro Tanaka ,  Takayuki Inoue ,  Hideomi Suzawa ,  Yasuhiko Takemura

    IPC分类号： H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  G11C16/00 ,  H01L29/788 ,  H01L29/49

    CPC分类号： H01L29/7869 ,  G11C11/24 ,  G11C16/00 ,  G11C16/0466 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78696 ,  H01L29/7881

    摘要： A method for manufacturing a semiconductor device with adjusted threshold is provided. In a semiconductor device including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is provided, a charge trap layer provided between the first gate electrode and the semiconductor, and a gate insulating layer provided between the second gate electrode and the semiconductor, a threshold is increased by trapping electrons in the charge trap layer by keeping a potential of the first gate electrode at a potential higher than a potential of the source or drain electrode for 1 second or more while heating. After the threshold adjustment process, the first gate electrode is removed or insulated from other circuits. Alternatively, a resistor may be provided between the first gate electrode and other circuits.

    摘要翻译： 提供一种用于制造具有调节阈值的半导体器件的方法。 在包括半导体，与半导体电连接的源电极或漏电极的半导体器件中，设置有半导体的第一栅电极和第二栅电极，设置在第一栅电极和半导体之间的电荷陷阱层，以及 设置在第二栅电极和半导体之间的栅极绝缘层，通过将第一栅电极的电位保持在高于源电极或漏电极的电位的电位为1，通过在电荷陷阱层中俘获电子来增加阈值 第二次或多次加热。 在阈值调整处理之后，第一栅电极被去除或与其它电路绝缘。 或者，可以在第一栅极电极和其它电路之间设置电阻器。