公开(公告)号：US08890252B2

公开(公告)日：2014-11-18

申请号：US13190798

申请日：2011-07-26

申请人： Hirotaka Saikaku ,  Tsuyoshi Yamamoto ,  Shoji Mizuno ,  Masakiyo Sumitomo ,  Tetsuo Fujii ,  Jun Sakakibara ,  Hitoshi Yamaguchi ,  Yoshiyuki Hattori ,  Rie Taguchi ,  Makoto Kuwahara

发明人： Hirotaka Saikaku ,  Tsuyoshi Yamamoto ,  Shoji Mizuno ,  Masakiyo Sumitomo ,  Tetsuo Fujii ,  Jun Sakakibara ,  Hitoshi Yamaguchi ,  Yoshiyuki Hattori ,  Rie Taguchi ,  Makoto Kuwahara

IPC分类号： H01L21/70 ,  H01L21/78 ,  H01L29/739 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/861 ,  H02M7/00

CPC分类号： H01L29/7813 ,  H01L27/0629 ,  H01L27/0635 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4983 ,  H01L29/66734 ,  H01L29/7391 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/7805 ,  H01L29/7819 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/861 ,  H01L2924/0002 ,  H02M7/003 ,  H01L2924/00

摘要： A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.

摘要翻译： 一种半导体器件包括：具有漂移层的开关元件; 基地区 在基极区域中的元件侧第一杂质区域; 夹在所述第一杂质区域和所述漂移层之间的元件侧栅电极; 接触漂移层的第二杂质区; 与元件侧第一杂质区域和基极区域耦合的元件侧第一电极; 以及与所述第二杂质区域耦合的元件侧第二电极以及具有：第一导电层的FWD; 第二导电层; 耦合到所述第二导电层的二极管侧第一电极; 耦合到所述第一导电层的二极管侧第二电极; 第二导电层中的二极管侧第一杂质区; 以及夹在第一杂质区域和第一导电层之间的第二导电层中的二极管侧栅电极，并具有作为过剩载流子注入抑制栅极的第一栅极电极。

公开(公告)号：US20060071242A1

公开(公告)日：2006-04-06

申请号：US11235495

申请日：2005-09-26

申请人： Ferruccio Frisina ,  Giuseppe Ferla ,  Angelo Magri

发明人： Ferruccio Frisina ,  Giuseppe Ferla ,  Angelo Magri

IPC分类号： H01L29/768

CPC分类号： H01L29/66666 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/417 ,  H01L29/41708 ,  H01L29/41716 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66128 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7322 ,  H01L29/7398 ,  H01L29/7809 ,  H01L29/8611

摘要： A vertical conduction electronic power device includes respective gate, source and drain areas, realized in an epitaxial layer arranged on a semiconductor substrate. The respective gate, source and drain metallizations may be realized by a first metallization level. The gate, source and drain terminals or pads may be realized by a second metallization level. The device is configured as a set of modular areas extending parallel to each other, each having a rectangular elongate source area perimetrically surrounded by a narrow gate area, and separated from each other by regions with the drain area extending parallel and connected at the opposite ends thereof to a second closed region with the drain area forming a device outer peripheral edge. A sinker structure extends perpendicularly to the substrate and may be formed by a grid of sinkers located below both the first parallel regions and the second closed region to favor a conductive channel for a current coming from the source area and directed towards the drain area across the substrate.

摘要翻译： 垂直导电电子功率器件包括在布置在半导体衬底上的外延层中实现的相应的栅极，源极和漏极区域。 相应的栅极，源极和漏极金属化可以通过第一金属化水平来实现。 栅极，源极和漏极端子或焊盘可以通过第二金属化水平来实现。 该装置被配置为一组彼此平行延伸的模块化区域，每个模块区域具有由狭窄的栅极区域周边围绕的矩形细长源区域，并且彼此分开，其中漏区域在相对端平行延伸并连接 其具有形成装置外周边缘的第二封闭区域。 沉降片结构垂直于衬底延伸，并且可以由位于第一平行区域和第二闭合区域下方的沉陷片形成，以便有助于来自源区域的电流的导电通道，并且引导通过漏极区域 基质。

公开(公告)号：US20030214012A1

公开(公告)日：2003-11-20

申请号：US10430569

申请日：2003-05-05

申请人： IXYS Corporation

发明人： Ulrich Kelberlau ,  Nathan Zommer

IPC分类号： H01L029/00

CPC分类号： H01L29/66712 ,  H01L29/0657 ,  H01L29/41766 ,  H01L29/66136 ,  H01L29/7398 ,  H01L29/7809 ,  H01L29/861 ,  H01L2224/16225 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00

摘要： A power device includes a substrate assembly including an upper surface and a lower surface. The substrate assembly includes a first layer and a second layer. The first layer overlies the second layer and has different conductivity than the second layer. A first electrode is provided proximate the upper surface. A second electrode is provided proximate the upper surface and is spaced apart from the first electrode. The second layer is configured to provide a current path between the first and second electrodes.

摘要翻译： 功率器件包括包括上表面和下表面的衬底组件。 衬底组件包括第一层和第二层。 第一层覆盖第二层并且具有与第二层不同的导电性。 第一电极靠近上表面设置。 第二电极靠近上表面设置并且与第一电极间隔开。 第二层被配置为在第一和第二电极之间提供电流路径。

公开(公告)号：US6023078A

公开(公告)日：2000-02-08

申请号：US67664

申请日：1998-04-28

申请人： Bantval Jayant Baliga

发明人： Bantval Jayant Baliga

IPC分类号： H01L29/24 ,  H01L29/74 ,  H01L29/747 ,  H01L29/749 ,  H01L31/0256

CPC分类号： H01L29/1608 ,  H01L29/7398 ,  H01L29/7436 ,  H01L29/747 ,  H01L29/749 ,  H01L29/7828 ,  H01L29/1604

摘要： Silicon carbide power devices include a semiconductor substrate of first conductivity type (e.g., N-type) having a face thereon and a blocking voltage supporting region of first conductivity type therein extending to the face. The voltage supporting region is designed to have a much lower majority carrier conductivity than an underlying and highly conductive "bypass" portion of the semiconductor substrate. This bypass portion of the substrate supports large lateral currents with low on-state voltage drop. First and second semiconductor devices are also provided having respective first and second active regions of first conductivity type therein. These first and second active regions extend on opposing sides of the voltage supporting region and are electrically coupled to the bypass portion of the semiconductor substrate which underlies and extends opposite the voltage supporting region relative to the face of the substrate. These first and second semiconductor devices are configured to provide bidirectional I-V characteristics by facilitating conduction in the first and third quadrants. A plurality of spaced regions of lower conductivity than the voltage supporting region are also formed in the voltage supporting region and extend to the face. These plurality of spaced regions extend opposite the bypass portion of the substrate and enhance the blocking voltage capability of the voltage supporting region.

摘要翻译： 碳化硅功率器件包括其上具有面的第一导电类型（例如N型）的半导体衬底和其中延伸到面的第一导电类型的阻挡电压支撑区域。 电压支撑区域被设计成具有比半导体衬底的下层和高导电性“旁路”部分低得多的载流子导电性。 衬底的该旁路部分支持具有低导通状态电压降的大横向电流。 还提供了第一和第二半导体器件，其中具有第一和第二有源区的第一导电类型。 这些第一和第二有源区域在电压支撑区域的相对侧上延伸，并且电耦合到半导体衬底的旁路部分，该旁路部分位于与基板的表面相对的电压支撑区域的下方并延伸。 这些第一和第二半导体器件被配置为通过促进第一和第三象限中的导通来提供双向I-V特性。 在电压支撑区域中还形成有比电压支撑区域低的导电性的多个间隔区域并且延伸到面部。 这些多个间隔区域与衬底的旁路部分相对地延伸，并增强了电压支撑区域的阻断电压能力。

公开(公告)号：US5689121A

公开(公告)日：1997-11-18

申请号：US480389

申请日：1995-06-07

申请人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

发明人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/745 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/7455 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/0696 ,  H01L29/4236

摘要： An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.

摘要翻译： 绝缘栅半导体器件包括P型发射极层，形成在P型发射极层上的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。 形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。 覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。 在一些沟槽之间的沟道区域中，在P型基极层的表面形成有与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。 连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。

公开(公告)号：US5621229A

公开(公告)日：1997-04-15

申请号：US434243

申请日：1995-05-04

申请人： Qin Huang

发明人： Qin Huang

IPC分类号： H01L29/739 ,  H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L29/78 ,  H01L29/861 ,  H01L23/58

CPC分类号： H01L29/7395 ,  H01L29/7398 ,  H01L29/7436 ,  H01L29/7455 ,  H01L29/749 ,  H01L2924/0002

摘要： A semiconductor device which reduces the turn-off time and the accompanying switching loss in a switching semiconductor device in which conductivity modulation is used to provide a low ON-state voltage. The conductivity modulation is provided by injection of minority carriers. A minority carrier injection-control structure is provided in part of a semiconductor device to change the polarity of a voltage applied to a gate electrode to start or stop the injection of minority carriers. During the ON-state, minority carriers are injected to obtain a low ON-state voltage, while during the OFF-state, the injection of minority carriers are stopped and a channel for majority carriers is formed to eliminate the accumulation of excess carriers and to accelerate discharge, thereby reducing the turn-off time and thus the switching loss.

摘要翻译： 一种降低开关半导体器件中的关断时间和伴随的开关损耗的半导体器件，其中使用电导率调制来提供低导通状态电压。 通过注入少数载流子提供电导率调制。 在半导体器件的一部分中提供少数载流子注入控制结构，以改变施加到栅电极的电压的极性，以启动或停止少数载流子的注入。 在ON状态下，注入少量载流子以获得低导通状态电压，而在OFF状态期间，停止少数载流子的注入，形成多数载流子的沟道以消除过量载流子的积累，并且 加速放电，从而减少关断时间，从而减少开关损耗。

公开(公告)号：US5559348A

公开(公告)日：1996-09-24

申请号：US460942

申请日：1995-06-05

申请人： Kiyoto Watabe ,  Ikunori Takata ,  Masana Harada

发明人： Kiyoto Watabe ,  Ikunori Takata ,  Masana Harada

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/739 ,  H01L29/786 ,  H01L29/74 ,  H01L23/58 ,  H01L27/01

CPC分类号： H01L29/0619 ,  H01L29/7394 ,  H01L29/7398 ,  H01L2924/0002

摘要： A semiconductor device which allows an ON-state voltage to be lower than that of a conventional device and a method of manufacturing such a device. In this semiconductor device, a gate electrode is formed to have a planar area of its region covering a first base layer larger than that of its region covering a second base layer, thereby increasing a cathode short-circuit ratio of a cathode-shorted diode equivalent to this semiconductor device. As a result, a lower voltage than conventional ON-state can be obtained.

摘要翻译： 允许ON状态电压低于常规器件的半导体器件和制造这种器件的方法。 在该半导体装置中，栅电极形成为具有覆盖比覆盖第二基极层的区域大的第一基极层的区域的平面区域，由此增加阴极短路二极管等效电极的阴极短路比 到该半导体器件。 结果，可以获得比常规ON状态更低的电压。

公开(公告)号：US5329142A

公开(公告)日：1994-07-12

申请号：US925870

申请日：1992-08-07

申请人： Mitsuhiko Kitagawa ,  Ichiro Omura

发明人： Mitsuhiko Kitagawa ,  Ichiro Omura

IPC分类号： H01L29/74 ,  H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/745 ,  H01L29/749 ,  H01L29/78 ,  H01L21/36 ,  H01L21/74

CPC分类号： H01L29/7455 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/0696 ,  H01L29/4236

摘要： A self turn-off power semiconductor device includes a P type emitter layer, a high resistive N type base layer, a P type base layer and a MOS channel structure for injecting electrons into the N type base layer. A series of trench-like grooves are formed in the top surface of a substrate constituting the N type base layer at a constant interval. Insulated gate electrodes are buried in these grooves. The injection efficiency of electrons into the base layer is enhanced by locally controlling the flow of holes in the N type base layer. Controlling the flow of holes is achieved by specifically arranging the width of a hole-bypass path among the grooves, the trench width and the placement distance of the grooves, thereby causing the accumulation of carriers to increase in the base layer to decrease the on-resistance of the device.

摘要翻译： 自关断功率半导体器件包括用于将电子注入到N型基极层中的P型发射极层，高电阻N型基极层，P型基极层和MOS沟道结构。 在构成N型基底层的基板的上表面中以一定间隔形成一系列沟槽状的沟槽。 绝缘栅电极被埋在这些槽中。 通过局部地控制N型基底层中的空穴流动，提高了电子进入基层的注入效率。 通过在凹槽之间特别设置孔旁路径的宽度，槽的沟槽宽度和布置距离来实现孔的流动控制，从而使载流子的积聚增加基底层， 设备的电阻。

公开(公告)号：US5253156A

公开(公告)日：1993-10-12

申请号：US647415

申请日：1991-01-29

申请人： Naoki Sakurai ,  Mutsuhiro Mori ,  Hidetoshi Arakawa ,  Kenichi Onda ,  Hideki Miyazaki ,  Akihiko Kanouda

发明人： Naoki Sakurai ,  Mutsuhiro Mori ,  Hidetoshi Arakawa ,  Kenichi Onda ,  Hideki Miyazaki ,  Akihiko Kanouda

IPC分类号： H01L21/762 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/06 ,  H01L29/739 ,  H01L29/872 ,  H02M7/00 ,  H02M7/5387 ,  H02P6/08 ,  H02M3/335 ,  H02M7/521

CPC分类号： H01L29/0696 ,  H01L21/76297 ,  H01L27/0635 ,  H01L29/0692 ,  H01L29/7394 ,  H01L29/7398 ,  H01L29/872 ,  H02M7/003 ,  H02M7/5387 ,  H02P6/085

摘要： A semiconductor integrated circuit unit, suitable for the control of a motor, has an integrated structure within the same semiconductor substrate, comprising an inverter circuit, drive circuits for driving the switching elements of the inverter circuit, an internal power source circuit for supplying power to the drive circuits which drive the upper arm side of the inverter circuit, and a logical circuit for transmitting a signal to the drive circuits which drive the upper arm side of the inverter circuit.

摘要翻译： 适用于电动机控制的半导体集成电路单元具有在同一半导体衬底内的集成结构，包括逆变器电路，用于驱动逆变器电路的开关元件的驱动电路，用于向 驱动逆变器电路的上臂侧的驱动电路，以及用于向驱动逆变器电路的上臂侧的驱动电路发送信号的逻辑电路。

公开(公告)号：US5155574A

公开(公告)日：1992-10-13

申请号：US663433

申请日：1991-03-01

申请人： Hiroshi Yamaguchi

发明人： Hiroshi Yamaguchi

IPC分类号： H01L29/06 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/0623 ,  H01L29/0619 ,  H01L29/7398 ,  H01L29/7809

摘要： A discrete array (30) of p-type regions (31) surrounding channel regions of n-channel MOSFET cells is provided in a drain region of the MOSFET cells. The p-type regions have depth corresponding to the depth of p-type areas (5) defining the channels. A depletion layer (F1) which is generated and extends from the channel regions through application of a voltage is stretched by the p-type regions, so that the electric field in the depletion layer is weakened. As a result, anti-breakdown ability of the MOSFET cells is improved. The discrete arrangement of the p-type regions is required in order to obtain current path between the channels and n-type drain regions (4).

摘要翻译： 在MOSFET单元的漏极区域中提供围绕n沟道MOSFET单元的沟道区域的p型区域（31）的离散阵列（30）。 p型区域具有对应于限定通道的p型区域（5）的深度的深度。 通过施加电压而从通道区域产生并延伸的耗尽层（F1）被p型区域拉伸，使得耗尽层中的电场减弱。 结果，提高了MOSFET电池的抗击穿能力。 为了获得通道与n型漏极区域（4）之间的电流路径，需要p型区域的离散布置。