公开(公告)号：US20150003000A1

公开(公告)日：2015-01-01

申请号：US13928796

申请日：2013-06-27

Applicant: Rahul N. MANEPALLI ,  Hamid R. AZIMI ,  John S. GUZEK

Inventor： Rahul N. MANEPALLI ,  Hamid R. AZIMI ,  John S. GUZEK

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/56

CPC classification number: H01L23/3121 ,  H01L21/561 ,  H01L21/568 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/50 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/96 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/3511 ,  H05K3/0097 ,  H05K3/4679 ,  H05K3/4682 ,  H05K2201/09918 ,  H05K2203/1536 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: Methods of forming molded panel coreless package structures are described. Those methods and structures may include fabrication of embedded die packages using large panel format and use of molding to improve rigidity of the panel, as well as to embed the die in a non-sacrificial mold material. The methods and structures described include methods for manufacturing thin, coreless substrate architectures which possess low warpage.

Abstract translation: 描述形成模制板无芯封装结构的方法。 这些方法和结构可以包括使用大面板格式制造嵌入式模具封装并使用模制来提高面板的刚度，以及将模具嵌入非牺牲模具材料中。 所描述的方法和结构包括制造具有低翘曲的薄的无芯基板结构的方法。

公开(公告)号：US08921706B2

公开(公告)日：2014-12-30

申请号：US13823700

申请日：2010-10-01

Applicant: Mitsuaki Toda ,  Yoshio Imamura ,  Takuya Hasegawa

Inventor： Mitsuaki Toda ,  Yoshio Imamura ,  Takuya Hasegawa

IPC: H05K1/16 ,  H05K1/18 ,  H05K3/32 ,  H05K1/02

CPC classification number: H05K1/182 ,  H05K1/0269 ,  H05K1/188 ,  H05K3/32 ,  H05K2201/09918 ,  H05K2201/10204 ,  H05K2201/10636 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/4913

Abstract: A component-embedded substrate includes an electrically insulating base (11) of resin, an electric or electronic embedded component (8) and a dummy embedded component (7) both embedded in the insulating base (11), a conductor pattern (18) formed on at least one side of the insulating base (11) and connected directly to or indirectly via a connection layer (6) to the embedded component (8) and the dummy embedded component (7), and a mark (10) formed on a surface of the dummy embedded component (7) and used as a reference when the conductor pattern (18) is formed, whereby positional accuracy of the conductor pattern (18) relative to the embedded component (8) can be improved.

Abstract translation: 部件嵌入式基板包括树脂电绝缘基座（11），嵌入在绝缘基座（11）中的电气或电子嵌入式部件（8）和虚拟嵌入部件（7），形成有导体图案（18） 在所述绝缘基体（11）的至少一侧上并且直接连接到所述嵌入部件（8）和所述虚拟嵌入部件（7）的连接层（6）或间接连接，以及形成在所述绝缘基体 并且当形成导体图案（18）时用作参考，从而能够提高导体图案（18）相对于嵌入部件（8）的位置精度。

公开(公告)号：US20140332162A1

公开(公告)日：2014-11-13

申请号：US14341901

申请日：2014-07-28

Applicant: ANTHONY FARACI ,  Gary N. SORTINO

Inventor： ANTHONY FARACI ,  Gary N. SORTINO

IPC: H05K3/46

CPC classification number: H05K3/4638 ,  H05K1/0269 ,  H05K3/00 ,  H05K3/4691 ,  H05K2201/09918 ,  H05K2203/06 ,  H05K2203/065 ,  H05K2203/101 ,  H05K2203/107 ,  H05K2203/1476 ,  H05K2203/166 ,  Y10T29/49126 ,  Y10T29/49213 ,  Y10T29/53087 ,  Y10T29/5317

Abstract: The present invention relates to a pin-less registration and inductive heating system involving the use of a pre-alignment station for imaging an initial position of a laminate element, an imaging and computer operation control system for determining a required correction factor between an alignment of the laminate element at the pre-alignment station and a preferred stack orientation for the laminate element, and an alignment and transfer system for securely gripping, transferring, and repositioning a laminate element from a top position to the preferred stack orientation employing a preferred four-axis orientation.

Abstract translation: 本发明涉及一种无针对配准和感应加热系统，其涉及使用用于对层压元件的初始位置进行成像的预对准工位，成像和计算机操作控制系统，用于确定所需的校正因子， 预对准工位的叠层元件以及用于层压元件的优选堆叠方向，以及用于使用优选的四层结构将层压元件从顶部位置牢固地夹紧，转移和重新定位到优选堆叠方向的对准和传送系统， 轴方向。

公开(公告)号：US08863375B2

公开(公告)日：2014-10-21

申请号：US13393697

申请日：2010-09-01

Applicant: Christoph Thumser ,  Gerhard Freydl

Inventor： Christoph Thumser ,  Gerhard Freydl

IPC: H05K3/30 ,  H05K3/00 ,  H05K1/14 ,  H05K1/02

CPC classification number: H05K3/305 ,  H05K1/0269 ,  H05K1/142 ,  H05K1/181 ,  H05K3/0097 ,  H05K2201/09063 ,  H05K2201/09145 ,  H05K2201/09918 ,  H05K2201/10598 ,  H05K2203/0169 ,  H05K2203/167 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T156/1089

Abstract: The invention relates to a method for connecting a plurality of elements for a circuit board, comprising the following steps: providing the elements of a circuit board to be connected to each other, the elements having contours adapted to each other; arranging the elements to be connected to each other in close proximity in at least one of two peripheral areas that have complementary contours, while maintaining a distance between opposing peripheral areas; and mechanically connecting the opposing peripheral areas by means of at least one sub-area thereof in order to connect the elements of the circuit board to be connected to each other. Furthermore, a circuit board produced from a plurality of elements connected to each other is provided.

Abstract translation: 本发明涉及一种用于连接电路板的多个元件的方法，包括以下步骤：提供要彼此连接的电路板的元件，所述元件具有彼此适配的轮廓; 将彼此连接的元件彼此紧密地布置在具有互补轮廓的两个外围区域中的至少一个中，同时保持相对的外围区域之间的距离; 并且通过其至少一个子区域机械地连接相对的外围区域，以将要连接的电路板的元件连接起来。 此外，提供了由彼此连接的多个元件制造的电路板。

公开(公告)号：US20140299367A1

公开(公告)日：2014-10-09

申请号：US14355558

申请日：2011-11-08

Applicant: Yoshio Imamura

Inventor： Yoshio Imamura

IPC: H05K13/04 ,  H05K1/18

CPC classification number: H05K13/0469 ,  H01L21/4846 ,  H01L21/568 ,  H01L23/145 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/2741 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32245 ,  H01L2224/82039 ,  H01L2224/82132 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2924/14 ,  H05K1/184 ,  H05K1/188 ,  H05K3/007 ,  H05K3/4602 ,  H05K2201/09918 ,  H05K2203/1469 ,  H05K2203/167 ,  Y10T29/49135

Abstract: The method includes forming an annular seat and main marks on a metal layer simultaneously so that the annular seat opposes with a terminal of an electronic component when the component is placed above the annular seat at a subsequent step; then positioning the electronic component in a mounting expected region using the main marks and mounting the electronic component with an adhesive layer therebetween; then burying the electronic component and the main marks in an insulating substrate; then removing part of the metal layer and thereby forming first and second windows; then irradiating the adhesive layer with laser using the exposed main marks thereby forming a laser via hole; and then filling the laser via hole with copper and forming a wiring pattern from the metal layer electrically connected to the terminal through a conductive via.

Abstract translation: 该方法包括在金属层上同时形成环形座和主标记，使得当在随后的步骤中将元件放置在环形座上方时，环形座与电子元件的端子相对; 然后使用主标记将电子部件定位在安装预期区域中，并且在其间具有粘合剂层来安装电子部件; 然后将电子部件和主要标记埋入绝缘基板中; 然后去除金属层的一部分，从而形成第一和第二窗口; 然后使用暴露的主标记用激光照射粘合剂层，从而形成激光通孔; 然后用铜填充激光通孔，并通过导电通孔从与端子电连接的金属层形成布线图案。

公开(公告)号：US08851356B1

公开(公告)日：2014-10-07

申请号：US13158149

申请日：2011-06-10

Applicant: Henry V. Holec ,  Wm. Todd Crandell ,  Eric Henry Holec

Inventor： Henry V. Holec ,  Wm. Todd Crandell ,  Eric Henry Holec

IPC: B23K31/02

CPC classification number: H05K3/363 ,  B23K1/0016 ,  B23K37/04 ,  F21Y2107/30 ,  F21Y2115/10 ,  H01R4/02 ,  H01R12/61 ,  H05K1/0269 ,  H05K1/118 ,  H05K1/144 ,  H05K1/147 ,  H05K1/189 ,  H05K2201/0311 ,  H05K2201/058 ,  H05K2201/09481 ,  H05K2201/09918 ,  H05K2201/10106 ,  H05K2203/0195 ,  H05K2203/0228 ,  H05K2203/043 ,  H05K2203/16

Abstract: Embodiments of the invention include flexible circuit board interconnections and methods regarding the same. In an embodiment, the invention includes a method of connecting a plurality of flexible circuit boards together comprising the steps applying a solder composition between an upper surface of a first flexible circuit board and a lower surface of a second flexible circuit board; holding the upper surface of the first flexible circuit board and the lower surface of the second flexible circuit board together; and reflowing the solder composition with a heat source to bond the first flexible circuit board and the second flexible circuit board together to form a flexible circuit board strip having a length longer than either of the first flexible circuit board or second flexible circuit board separately. In an embodiment the invention includes a circuit board clamp for holding flexible circuit boards together, the clamp including a u-shaped fastener; a spring tension arm connected to the u-shaped fastener; and an attachment mechanism connected to the spring tension arm. Other embodiments are also included herein.

Abstract translation: 本发明的实施例包括柔性电路板互连和相关的方法。 在一个实施例中，本发明包括将多个柔性电路板连接在一起的方法，包括在第一柔性电路板的上表面和第二柔性电路板的下表面之间施加焊料组合物的步骤; 将第一柔性电路板的上表面和第二柔性电路板的下表面保持在一起; 并且用热源回流焊料组合物，以将第一柔性电路板和第二柔性电路板结合在一起，以分别形成长度大于第一柔性电路板或第二柔性电路板的长度的柔性电路板条。 在一个实施例中，本发明包括用于将柔性电路板保持在一起的电路板夹，所述夹具包括u形紧固件; 连接到U形紧固件的弹簧张力臂; 以及连接到弹簧张力臂的连接机构。 本文还包括其它实施例。

公开(公告)号：US20140293258A1

公开(公告)日：2014-10-02

申请号：US14224712

申请日：2014-03-25

Applicant: TDK CORPORATION

Inventor： Naozumi ISHIKAWA ,  Fumio WATANABE ,  Hiroshi KAMIYAMA

IPC: H05K3/06

CPC classification number: H05K3/0008 ,  H05K1/0269 ,  H05K1/165 ,  H05K3/0002 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2203/056 ,  H05K2203/166

Abstract: A first alignment mark is given to a substrate, and a second alignment mark is given to a mask. The mask forms an electronic circuit pattern on the substrate. A control unit performs alignment of the mask and the substrate based on the first and second alignment marks. The second alignment mark is formed to surround the first alignment mark. The second alignment mark has a step pattern therein.

Abstract translation: 向基板施加第一对准标记，向掩模施加第二对准标记。 掩模在基板上形成电子电路图案。 控制单元基于第一和第二对准标记执行掩模和基板的对准。 第二对准标记形成为围绕第一对准标记。 第二对准标记中具有台阶图案。

公开(公告)号：US08807026B2

公开(公告)日：2014-08-19

申请号：US12751408

申请日：2010-03-31

Applicant: Armand Bettinelli

Inventor： Armand Bettinelli

IPC: B41M1/12

CPC classification number: H05K3/1216 ,  B41F15/0881 ,  B41F15/12 ,  B41F33/0081 ,  B41M1/12 ,  B41M3/006 ,  B41P2215/112 ,  B41P2215/50 ,  B41P2233/52 ,  H01L31/022425 ,  H05K1/0269 ,  H05K3/0008 ,  H05K3/245 ,  H05K2201/09918 ,  H05K2203/163

Abstract: Method for printing on a wafer (1) by screen-printing, characterized in that it comprises the following steps: producing at least two first test-patterns (5a-5d) on the surface (4) of the wafer (1); printing at least four second test-patterns (6a-6d), distinct from the at least two first test-patterns (5a-5d), during printing on the surface (4) of the wafer (1) by screen-printing; measuring the actual distance obtained on the surface (4) of the wafer (1) between the first test-patterns (5a-5d) and the second test-patterns (6a-6d); comparing this actual distance with a theoretical distance in order to deduce therefrom the offset of the screen-printing screen (25) of the printing.

Abstract translation: 通过丝网印刷在晶片（1）上印刷的方法，其特征在于包括以下步骤：在晶片（1）的表面（4）上产生至少两个第一测试图案（5a-5d）; 在通过丝网印刷在晶片（1）的表面（4）上印刷期间印刷与所述至少两个第一测试图案（5a-5d）不同的至少四个第二测试图案（6a-6d）; 测量在第一测试图案（5a-5d）和第二测试图案（6a-6d）之间在晶片（1）的表面（4）上获得的实际距离; 将该实际距离与理论距离进行比较，以便从其推导出打印的丝网印刷屏幕（25）的偏移。

公开(公告)号：US20140217581A1

公开(公告)日：2014-08-07

申请号：US14248380

申请日：2014-04-09

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Hijiri SUMII ,  Manabu NAKAHORI

IPC: H01L23/00

CPC classification number: H01L24/10 ,  H01L23/315 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2924/181 ,  H05K1/0269 ,  H05K1/0306 ,  H05K3/0097 ,  H05K3/303 ,  H05K2201/09918 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: An electronic component includes a plurality of electrodes provided in a rectangular or substantially rectangular box-shaped area on an upper surface of a substrate, an electronic component element mounted on the substrate by flip-chip bonding, and an identification mark. The identification mark is provided between a first electrode, which is arranged along one side of the rectangular or substantially rectangular box-shaped area, and a second electrode, which is adjacent to the first electrode along the one side, of the plurality of electrodes provided on the upper surface of the substrate, and is located on or outside a line connecting the outer side edges of the first and second electrodes.

Abstract translation: 电子部件包括设置在基板的上表面上的矩形或大致矩形的箱形区域中的多个电极，通过倒装芯片接合安装在基板上的电子部件元件和识别标记。 识别标记设置在沿着矩形或大致矩形的箱形区域的一侧布置的第一电极和与设置的多个电极中的沿着一侧的第一电极相邻的第二电极 在基板的上表面上，并且位于连接第一和第二电极的外侧边缘的线之上或之外。

公开(公告)号：US08774576B2

公开(公告)日：2014-07-08

申请号：US13215746

申请日：2011-08-23

Applicant: Takashi Shiraishi

Inventor： Takashi Shiraishi

IPC: G02B6/12 ,  G02B6/32 ,  H05K1/02 ,  H05K1/18 ,  G02B6/42 ,  H05K1/14

CPC classification number: H05K1/0274 ,  G02B6/42 ,  G02B6/4206 ,  G02B6/4214 ,  G02B6/4224 ,  G02B6/4246 ,  G02B6/4249 ,  G02B6/4281 ,  H05K1/147 ,  H05K1/189 ,  H05K2201/09918 ,  H05K2201/10121 ,  H05K2203/166 ,  Y10T29/49155

Abstract: A an optical module includes a circuit board provided with an optical element selected from a light-receiving element and/or a light-emitting element; a lens where light from the optical element passes through; an alignment mark serving as an indicator for alignment with the optical element; and an optical waveguide formed to input/output light into/from the optical element through the lens.

Abstract translation: 光学模块包括设置有从光接收元件和/或发光元件中选择的光学元件的电路板; 来自光学元件的光通过的透镜; 用作与光学元件对准的指示器的对准标记; 以及形成为通过透镜将光输入/输出光学元件的光波导。