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301.
公开(公告)号:US20240379452A1
公开(公告)日:2024-11-14
申请号:US18780679
申请日:2024-07-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Min-Yann Hsieh , Hua Feng Chen , Jhon Jhy Liaw
IPC: H01L21/8234 , H01L21/3105 , H01L21/762 , H01L27/088
Abstract: A semiconductor device includes. A first epi-layer and a second epi-layer are each located in a first region of the semiconductor device. A first dielectric fin is located between the first epi-layer and the second epi-layer. The first dielectric fin has a first dielectric constant. A third epi-layer and a fourth epi-layer are each located in a second region of the semiconductor device. A second dielectric fin is located between the third epi-layer and the fourth epi-layer. The second dielectric fin has a second dielectric constant that is less than the first dielectric constant.
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公开(公告)号:US20240379450A1
公开(公告)日:2024-11-14
申请号:US18780110
申请日:2024-07-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yi Chen Ho , Yiting Chang , Chi-Hsun Lin , Zheng-Yang Pan
IPC: H01L21/8234 , H01L21/02 , H01L21/762 , H01L27/088
Abstract: In an embodiment, a device includes: an isolation region on a substrate; a first semiconductor fin protruding above the isolation region; a second semiconductor fin protruding above the isolation region; and a dielectric fin between the first semiconductor fin and the second semiconductor fin, the dielectric fin protruding above the isolation region, the dielectric fin including: a first layer including a first dielectric material having a first carbon concentration; and a second layer on the first layer, the second layer including a second dielectric material having a second carbon concentration, the second carbon concentration greater than the first carbon concentration.
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公开(公告)号:US20240379442A1
公开(公告)日:2024-11-14
申请号:US18784531
申请日:2024-07-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Xusheng Wu , Ying-Keung Leung , Huiling Shang
IPC: H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/786
Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (S/D) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk S/D feature is separated from the substrate by a first air gap, and the bulk S/D feature is separated from the inner spacers by second air gaps.
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公开(公告)号:US20240379433A1
公开(公告)日:2024-11-14
申请号:US18782900
申请日:2024-07-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Pin-Wen Chen , Chia-Han Lai , Chih-Wei Chang , Mei-Hui Fu , Ming-Hsing Tsai , Wei-Jung Lin , Yu-Shih Wang , Ya-Yi Cheng , I-Li Chen
IPC: H01L21/768 , H01L21/285 , H01L21/3213 , H01L23/535
Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.
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公开(公告)号:US20240379428A1
公开(公告)日:2024-11-14
申请号:US18780044
申请日:2024-07-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Ming-Da Cheng , Tzy-Kuang Lee , Hao Chun Liu , Po-Hao Tsai , Chih-Hsien Lin , Ching-Wen Hsiao
IPC: H01L21/768 , H01L21/48 , H01L21/60 , H01L23/00 , H01L23/532
Abstract: A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.
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公开(公告)号:US20240379407A1
公开(公告)日:2024-11-14
申请号:US18783544
申请日:2024-07-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wen-Yen Chen , Li-Ting Wang , Wan-Chen Hsieh , Bo-Cyuan Lu , Tai-Chun Huang , Huicheng Chang , Yee-Chia Yeo
IPC: H01L21/762 , H01L21/02 , H01L21/764 , H01L21/768
Abstract: A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.
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公开(公告)号:US20240379364A1
公开(公告)日:2024-11-14
申请号:US18779365
申请日:2024-07-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yu-Jiun Peng , Hsiu-Hao Tsao , Shu-Han Chen , Chang-Jhih Syu , Kuo-Feng Yu , Jian-Hao Chen , Chih-Hao Yu , Chang-Yun Chang
IPC: H01L21/28 , H01L21/02 , H01L21/285 , H01L21/311 , H01L21/3115 , H01L21/8234 , H01L21/8238 , H01L29/08 , H01L29/423 , H01L29/45 , H01L29/49 , H01L29/66 , H01L29/78
Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.
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公开(公告)号:US20240377766A1
公开(公告)日:2024-11-14
申请号:US18783178
申请日:2024-07-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yen-Hui LI , Cheng-Han YEH , Tzung-Chi FU
Abstract: An extreme ultraviolet (EUV) photolithography system cleans debris from an EUV reticle. The system includes a cleaning electrode configured to be positioned adjacent the EUV reticle. The system includes a voltage source that helps draw debris from the EUV reticle toward the cleaning electrode by applying a voltage of alternating polarity to the cleaning electrode.
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公开(公告)号:US20240377755A1
公开(公告)日:2024-11-14
申请号:US18780081
申请日:2024-07-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Peter Yu , Chih-Tung Hsu , Kevin Wang , Chih-Chia Hu , Roger Chen
Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
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公开(公告)号:US20240377735A1
公开(公告)日:2024-11-14
申请号:US18783765
申请日:2024-07-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: An-Ren Zi , Joy Cheng , Ching-Yu Chang
IPC: G03F7/004
Abstract: A photoresist layer is formed over a wafer. The photoresist layer includes a metallic photoresist material and one or more additives. An extreme ultraviolet (EUV) lithography process is performed using the photoresist layer. The one or more additives include: a solvent having a boiling point greater than about 150 degrees Celsius, a photo acid generator, a photo base generator, a quencher, a photo de-composed base, a thermal acid generator, or a photo sensitivity cross-linker.
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