公开(公告)号：US20040031973A1

公开(公告)日：2004-02-19

申请号：US10446589

申请日：2003-05-27

Applicant: STMicroelectronics S.r.I

Inventor： Carlo Cognetti ,  Ubaldo Mastromatteo

IPC: H01L027/10

CPC classification number: H01L31/18 ,  H01L31/0203 ,  H01L31/02325 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/11 ,  H01L2224/29011 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2224/83 ,  H01L2224/05099

Abstract: A process for manufacturing encapsulated optical sensors, including the steps of: forming a plurality of mutually spaced optical sensors in a wafer of semiconductor material; bonding a plate of transparent material to the wafer so as to seal the optical sensors; and dividing the wafer into a plurality of dies, each comprising an optical sensor and a respective portion of the plate.

Abstract translation: 一种用于制造封装的光学传感器的方法，包括以下步骤：在半导体材料的晶片中形成多个相互间隔的光学传感器; 将透明材料板粘合到晶片上以便密封光学传感器; 并将晶片分成多个模具，每个模具包括光学传感器和板的相应部分。

公开(公告)号：US20040019814A1

公开(公告)日：2004-01-29

申请号：US10440044

申请日：2003-05-16

Applicant: STMicroelectronics SA ,  STMicroelectronics S.r.I.

Inventor： Francesco Pappalardo ,  Luigi Mantellassi

IPC: G06F001/26

CPC classification number: G06F9/30101 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  H01L23/34 ,  H01L2924/0002 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/171 ,  H01L2924/00

Abstract: A system-on-chip (SoC) architecture includes a plurality of blocks, each including a power control module to selectively control the power dissipated by the bloc. For each block, a power register is provided to receive power control instructions to selectively control the respective power control module. The system also includes a power control unit for writing respective power control instructions into the power control registers of the blocks, whereby the power dissipated is controlled individually and independently for each block under the centralized control of the power control unit. For each block, a power status register is also provided to receive status information concerning power control within the respective block. The power control unit reads the status instructions from such power status registers.

Abstract translation: 片上系统（SoC）架构包括多个块，每个块包括功率控制模块，用于选择性地控制由该块所耗散的功率。 对于每个块，提供功率寄存器以接收功率控制指令以选择性地控制相应的功率控制模块。 该系统还包括用于将各个功率控制指令写入块的功率控制寄存器的功率控制单元，由此在功率控制单元的集中控制下，对每个块单独且独立地控制功率消耗。 对于每个块，还提供功率状态寄存器以接收关于相应块内的功率控制的状态信息。 电源控制单元从这些电源状态寄存器读取状态指令。

公开(公告)号：US20040008549A1

公开(公告)日：2004-01-15

申请号：US10440043

申请日：2003-05-15

Applicant: STMicroelectronics S.r.I

Inventor： Rino Micheloni ,  Aldo Losavio

IPC: G11C007/00

CPC classification number: G11C29/82 ,  G11C29/846

Abstract: The memory device has a memory block, formed by a plurality of standard sectors and a redundancy portion; a control circuit, which controls programming and erasing of the data of the memory cells; and a correctness verifying circuit for the data stored in the memory cells. The correctness verifying circuit is enabled by the control circuit and generates an incorrect-datum signal in the event of detection of at least one non-functioning cell. The control circuit moreover activates redundancy, enabling the redundancy portion and storing redundancy data in a redundancy-memory stage in the presence of an incorrect datum. Various solutions are presented that implement column, row and sector redundancy, both in case of erasing and programming.

Abstract translation: 存储装置具有由多个标准扇区和冗余部分形成的存储块; 控制电路，其控制存储器单元的数据的编程和擦除; 以及用于存储在存储单元中的数据的正确性验证电路。 正确性验证电路由控制电路启用，并且在检测至少一个非功能单元的情况下产生不正确的基准信号。 此外，控制电路激活冗余，使冗余部分能够在存在不正确的数据的情况下将冗余数据存储在冗余存储器级中。 提出了实现列，行和扇区冗余的各种解决方案，无论在擦除和编程的情况下。

公开(公告)号：US20030235100A1

公开(公告)日：2003-12-25

申请号：US10426924

申请日：2003-04-29

Applicant: STMicroelectronics S.r.I.

Inventor： Luigi Pascucci

IPC: G11C007/00

CPC classification number: G11C16/3427 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/3418

Abstract: An NROM memory device, wherein the memory cells are provided with charge storage regions of insulating material, such as silicon nitride. The memory device includes a row decoder comprising a plurality of drivers; during programming, a first driver supplies a first voltage having a first value to a selected wordline, while the other drivers are configured so as to supply a second voltage having a second non-zero value, lower than the first value, to the other wordlines. Thereby, the gate-drain voltage drop of the deselected cells is reduced, and thus spurious erasing of the deselected cells connected to the selected bitline is reduced. Consequently, the reliability of the memory device is improved considerably and the life thereof is lengthened, thanks to the reduction in the charge injected into the charge storage region.

Abstract translation: 一种NROM存储器件，其中存储单元设置有诸如氮化硅的绝缘材料的电荷存储区域。 存储装置包括行解码器，其包括多个驱动器; 在编程期间，第一驱动器向所选择的字线提供具有第一值的第一电压，而其他驱动器被配置为将具有低于第一值的第二非零值的第二电压提供给其它字线 。 因此，取消选择的单元的栅极 - 漏极电压降降低，并且因此连接到所选位线的取消选择的单元的寄生擦除减少。 因此，由于注入到电荷存储区域的电荷减少，存储器件的可靠性显着提高并且寿命延长。

公开(公告)号：US20030231130A1

公开(公告)日：2003-12-18

申请号：US10172376

申请日：2002-06-14

Applicant: STMicroelectronics S.r.I.

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno ,  Francesca Girardi

IPC: H03M001/38 ,  H03M001/10

CPC classification number: H03M1/181 ,  H03M1/468

Abstract: A method of operating an SAR-type analog-to-digital converter to match the dynamic range of an input voltage signal to be converted with the full scale range of the converter, the converter including at least one array of binary weighted capacitors. The method includes the step of obtaining a digital gain code that represents the ratio between the full scale range and the dynamic range of the voltage signal to be converted, applying the voltage signal to be converted to the capacitor array so as to charge with the voltage signal to be converted only those array capacitors having the same binary weights as the bits of the gain code that have a selected binary value, and selectively coupling the capacitors of the array to one of a first and second predetermined reference voltage terminals according to an SAR technique, to obtain an output digital code corresponding to the input voltage signal.

Abstract translation: 一种操作SAR型模数转换器以匹配要转换的输入电压信号的动态范围与转换器的满量程范围的方法，所述转换器包括至少一个二进制加权电容器阵列。 该方法包括获得数字增益代码的步骤，该数字增益代码表示满量程范围和要转换的电压信号的动态范围之间的比率，将要转换的电压信号施加到电容器阵列，以便对电压进行充电 信号仅转换具有与具有选定二进制值的增益码的位相同的二进制权重的阵列电容器，并且根据SAR选择性地将阵列的电容器耦合到第一和第二预定参考电压端子之一 技术，以获得对应于输入电压信号的输出数字代码。

公开(公告)号：US20030222354A1

公开(公告)日：2003-12-04

申请号：US10406633

申请日：2003-04-02

Applicant: STMicroelectronics S.r.I.

Inventor： Ubaldo Mastromatteo ,  Paolo Ferrari

IPC: H01L029/00 ,  H01L029/40 ,  H01L021/4763 ,  H01L021/44 ,  H01L023/04 ,  H01L023/48 ,  H01L023/52

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05572 ,  H01L2224/13025 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The process for manufacturing a through insulated interconnection is performed by forming, in a body of semiconductor material, a trench extending from the front (of the body for a thickness portion thereof; filling the trench with dielectric material; thinning the body starting from the rear until the trench, so as to form an insulated region surrounded by dielectric material; and forming a conductive region extending inside said insulated region between the front and the rear of the body and having a higher conductivity than the first body. The conductive region includes a metal region extending in an opening formed inside the insulated region or of a heavily doped semiconductor region, made prior to filling of the trench.

Abstract translation: 通过绝缘互连制造的方法是通过在半导体材料体中形成从前部（其主体的厚度部分）延伸的沟槽;用电介质材料填充沟槽;从后面开始使身体变薄 直到形成由电介质材料包围的绝缘区域，形成在主体前后的绝缘区域内延伸的导电性区域，并具有比第1主体高的导电性，导电区域包括： 金属区域在形成在绝缘区域内的开口中延伸，或者在填充沟槽之前制成的重掺杂半导体区域。

公开(公告)号：US20030197217A1

公开(公告)日：2003-10-23

申请号：US10372044

申请日：2003-02-20

Applicant: STMicroelectronics S.r.I

Inventor： Luigi Pascucci

IPC: H01L021/336 ,  H01L029/788

CPC classification number: H01L29/7923 ,  G11C11/5671 ,  G11C16/0458 ,  G11C16/0475 ,  H01L21/28282

Abstract: An electrically-programmable memory cell programmed by means of injection of channel hot electrons into a charge-storage element capacitively coupled to a memory cell channel for modulating a conductivity thereof depending on a stored amount of charge. A first and a second spaced-apart electrode regions are formed in a semiconductor layer and define a channel region there between; at least one of the first and second electrode regions acts as a programming electrode of the memory cell. A control electrode is capacitively coupled to the charge-storage element. The charge-storage element is placed over the channel to substantially extend from the first to the second electrode regions, and is separated from the channel region by a dielectric layer. The dielectric layer has a reduced thickness in a portion thereof near the at least one programming electrode.

Abstract translation: 通过将通道热电子注入到电容耦合到存储单元通道的电荷存储元件来编程的电可编程存储单元，用于根据存储的电荷量来调制其电导率。 第一和第二间隔开的电极区域形成在半导体层中并在其间限定沟道区域; 第一和第二电极区域中的至少一个用作存储单元的编程电极。 控制电极电容耦合到电荷存储元件。 电荷存储元件放置在通道上，从第一至第二电极区域基本上延伸，并通过电介质层与沟道区分离。 电介质层在其至少一个编程电极附近的部分中具有减小的厚度。

公开(公告)号：US20030183869A1

公开(公告)日：2003-10-02

申请号：US10356351

申请日：2003-01-30

Applicant: STMicroelectronics S.r.I.

Inventor： Barbara Crivelli ,  Mauro Alessandri

IPC: H01L029/76

CPC classification number: H01L29/511 ,  H01L21/28273 ,  H01L21/3144

Abstract: A process manufactures an interpoly dielectric layer for non-volatile memory cells of a semiconductor device with an interpoly dielectric layer. The process begins with forming the tunnel oxide, and hence the amorphous or polycrystalline silicon layer, using conventional techniques. After the amorphous or polycrystalline silicon layer is surface cleansed and passivated, the surface of the polycrystalline layer is nitrided directly by using radical nitrogen. This is followed by the formation of the interpoly dielectric, either as an ONO layer or a single silicon layer, by means of the CVD technique. Masking to define the floating gate may be performed immediately before or after the direct nitridation step is carried out. The equivalent electrical thickness of the interpoly dielectric, obtained by combining the nitride oxide layer and by the following dielectric, does not exceed 130 Angstroms in either the ONO layer or the single silicon layer embodiment.

Abstract translation: 一种工艺制造用于具有多层电介质层的半导体器件的非易失性存储单元的互补电介质层。 该过程开始于使用常规技术形成隧道氧化物，因此形成非晶或多晶硅层。 在非晶或多晶硅层被表面清洁和钝化之后，多晶层的表面通过使用自由基氮直接氮化。 之后，通过CVD技术形成作为ONO层或单个硅层的互聚电介质。 可以在执行直接氮化步骤之前或之后立即执行用于限定浮动栅极的掩模。 通过组合氮氧化物层和随后的电介质获得的互聚电介质的等效电学厚度在ONO层或单硅层实施例中不超过130埃。

公开(公告)号：US20030147293A1

公开(公告)日：2003-08-07

申请号：US10328721

申请日：2002-12-23

Applicant: STMicroelectronics S.r.I.

Inventor： Antonino Geraci ,  Alberto Campisi ,  Lorenzo Bedarida ,  Simone Bartoli

IPC: G11C029/00

CPC classification number: G11C29/44

Abstract: An autotesting method of a cells matrix of a memory device is disclosed which comprises the steps of: reading the values contained in a plurality of the memory cells; comparing the read values with reference values; signalling mismatch of the read values with the reference values as an error situation; and storing the error situations. In the autotesting method, the reading, comparing, signalling, and storing steps are repeated for all the memory cells in an matrix column. The autotesting method according to the invention further comprises the steps of storing the positions of any columns having at least one one error situation; and repeating all of the preceding steps according to a step of scanning all the matrix columns.

Abstract translation: 公开了一种存储器件的单元矩阵的自动测试方法，其包括以下步骤：读取多个存储器单元中包含的值; 将读取的值与参考值进行比较; 读取值与参考值的信令不匹配作为错误情况; 并存储错误情况。 在自动测试方法中，对矩阵列中的所有存储单元重复读取，比较，信令和存储步骤。 根据本发明的自动测试方法还包括以下步骤：存储具有至少一个错误情况的任何列的位置; 并且根据扫描所有矩阵列的步骤重复所有前述步骤。

公开(公告)号：US20030123306A1

公开(公告)日：2003-07-03

申请号：US10325486

申请日：2002-12-19

Applicant: STMicroelectronics S.r.I.

Inventor： Salvatore Polizzi ,  Maurizio Perroni

IPC: G11C007/00

CPC classification number: G11C7/222 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2281

Abstract: The memory device of the invention outputs the read data in a time starting from the rising edge of the external clock that is shorter than that of other known devices, because the output buffer has an array of master-slave pairs of flip-flops synchronized by respective timing signals derived from the internal clock signal. The array receives data from the state machine through the second internal bus and provides the data to be output to the output stage of the buffer enabled by the state machine. A logic circuit generates timing signals for the master-slave flip-flops, respectively as logic NAND and logic AND of the internal clock signal and of an enabling signal of the output stage of the buffer generated by the state machine. Moreover, the memory device includes a circuit, synchronized by the internal clock signal, that introduces a delay of the enabling signal of the output stage of the buffer equivalent to a period of the internal clock signal.

Abstract translation: 本发明的存储器件在从外部时钟的上升沿开始的时间内比其它已知器件的存储器件输出读出的数据，因为输出缓冲器具有通过触发器同步的主 - 从对的阵列 从内部时钟信号导出的各个定时信号。 该阵列通过第二个内部总线从状态机接收数据，并将数据输出到由状态机启用的缓冲区的输出级。 逻辑电路产生主从触发器的定时信号，分别作为状态机产生的内部时钟信号和缓冲器的输出级的使能信号的逻辑“与”和逻辑“与”。 此外，存储器件包括由内部时钟信号同步的电路，其引入与内部时钟信号的周期相当的缓冲器的输出级的使能信号的延迟。