公开(公告)号：US20240371674A1

公开(公告)日：2024-11-07

申请号：US18769250

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Lien Linus LU ,  Cormac Michael O'CONNELL

IPC: H01L21/68 ,  B25J9/16 ,  B25J11/00 ,  H01L21/67 ,  H01L21/673

Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator comprising: a plurality of PUF cells, wherein each of the plurality of PUF cells comprises a first MOS transistor and a second MOS transistor, wherein terminal S of the first MOS transistor is connected to terminal D of the second MOS transistor at a dynamic node, terminal D of the first MOS transistor is coupled to a first bus and terminal G of the first NMOS transistor is coupled to a second bus, and terminals S and G of the second NMOS transistor are coupled to ground; a plurality of dynamic flip-flop (DFF) circuits wherein each of the plurality of DFF circuits is coupled to each of the plurality of PUF cells respectively; a population count circuit coupled to the plurality of DFF circuits; and an evaluation logic circuit having an input coupled to the population count circuit and an output coupled to the plurality of DFF circuits.

公开(公告)号：US20240371648A1

公开(公告)日：2024-11-07

申请号：US18773292

申请日：2024-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao KUNG ,  Hui-Chi HUANG ,  Kei-Wei CHEN ,  Yen-Ting Chen

IPC: H01L21/306 ,  B24B37/24 ,  H01L21/321

Abstract: Provided herein are polishing pads in which microcapsules that include a polymer material and are dispersed, as well as methods of making and using the same. Such microcapsules are configured to break open (e.g., when the polishing pad is damaged during the dressing process), which releases the polymer material. When contacted with ultraviolet light the polymer material at least partially cures, healing the damage to the polishing pad. Such polishing pads have a longer lifetime and a more stable remove rate when compared to standard polishing pads.

公开(公告)号：US20240371639A1

公开(公告)日：2024-11-07

申请号：US18771784

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chao ,  Chung-Cheng Wang ,  Chun-Kuang Chen

IPC: H01L21/027 ,  H01L21/66 ,  H01L21/67 ,  H05B1/02 ,  H05B3/24 ,  H05B3/68

Abstract: A test wafer is placed inside a baking module and is baked. Via one or more temperature sensors, a cumulative heat amount delivered to the test wafer during the baking is measured. The measured cumulative heat amount is compared with a predefined cumulative heat amount threshold. In response to the comparing indicating that the measured cumulative heat amount is within the predefined cumulative heat amount threshold, it is determined that the baking module is qualified for actual semiconductor fabrication. In response to the comparing indicating that the measured cumulative heat amount is outside of the predefined cumulative heat amount threshold, it is determined that the baking module is not qualified for actual semiconductor fabrication.

公开(公告)号：US20240369620A1

公开(公告)日：2024-11-07

申请号：US18505781

申请日：2023-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyu-Hua HSIAO ,  Chin-Yu LIN ,  Chien Fang HUANG ,  Kam Heng LEE ,  Jiun-Rong PAI

IPC: G01R31/28

Abstract: A method includes: positioning a wafer in a first probe chamber of a first probe apparatus by a robot arm, the first probe apparatus being adjacent a transfer rail, the robot arm, in operation, moving along the transfer rail; testing the wafer by the first probe apparatus; following the testing, transferring the wafer to an environmental buffer attached to the first probe chamber; cooling the wafer in the environmental buffer; and following the cooling, transferring the wafer from the environmental buffer to a second probe chamber of a second probe apparatus by the robot arm, the second probe apparatus being adjacent the transfer rail and offset from the first probe apparatus.

公开(公告)号：US12136566B2

公开(公告)日：2024-11-05

申请号：US17969396

申请日：2022-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Shih Wang ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

公开(公告)号：US12134555B2

公开(公告)日：2024-11-05

申请号：US18315799

申请日：2023-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Liu ,  Chia-Hua Chu ,  Chun-Wen Cheng

IPC: B81B7/00 ,  B81C1/00

Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.

公开(公告)号：US20240365559A1

公开(公告)日：2024-10-31

申请号：US18766899

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui ,  Yu-Ming Lin

IPC: H10B51/30 ,  H01L21/02 ,  H01L21/768 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B43/20 ,  H10B43/30 ,  H10B51/20 ,  H10B99/00

CPC classification number: H10B51/30 ,  H01L21/02565 ,  H01L21/02603 ,  H01L21/76816 ,  H01L21/76877 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/78391 ,  H01L29/78696 ,  H10B43/20 ,  H10B43/30 ,  H10B51/20 ,  H10B99/00

Abstract: 3D-NOR memory array devices and methods of manufacture are disclosed herein. A method includes forming a multi-layer stack over a substrate by forming alternating layers of an isolation material and a dummy material. An array of dummy nanostructures is formed in a channel region of the multi-layer stack by performing a wire release process. Once the nanostructures have been formed, a single layer of an oxide semiconductor material is deposited over and surrounds the dummy nanostructures. A memory film is then deposited over the oxide semiconductor material and a conductive wrap-around structure is formed over the memory film. Source/bit line structures may be formed by replacing the layers of the dummy material outside of the channel region with a metal fill material. A staircase conductor structure can be formed the source/bit line structures in a region of the multi-layer stack adjacent the memory array.

公开(公告)号：US20240365557A1

公开(公告)日：2024-10-31

申请号：US18770406

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chi On Chui

IPC: H10B51/20 ,  H01L21/28 ,  H01L29/78 ,  H01L29/786 ,  H10B51/00 ,  H10B51/10 ,  H10B51/30

CPC classification number: H10B51/20 ,  H01L29/40111 ,  H01L29/78391 ,  H01L29/785 ,  H01L29/78696 ,  H10B51/00 ,  H10B51/10 ,  H10B51/30

Abstract: A device includes a first channel; a second channel above the first channel; and a gate structure surrounding the first and second channels, wherein the gate structure includes a ferroelectric (FE) layer surrounding the first and second channels and a gate metal layer surrounding the FE layer. The device further includes two first electrodes connected to two sides of the first channel; two second electrodes connected to two sides of the second channel; a dielectric layer between the first and the second electrodes; and an inner spacer layer between the two first electrodes and the gate structure.

公开(公告)号：US20240363791A1

公开(公告)日：2024-10-31

申请号：US18766336

申请日：2024-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih Wei Sung ,  Chung-Bin Tseng ,  Keng-Ying Liao ,  Yen-Jou Wu ,  Po-Zen Chen ,  Su-Yu Yeh ,  Ching-Chung Su

IPC: H01L31/18 ,  H01L23/544 ,  H01L27/146

CPC classification number: H01L31/1876 ,  H01L23/544 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14683 ,  H01L27/14687 ,  H01L31/186 ,  H01L31/1888 ,  H01L2223/54426

Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.

公开(公告)号：US20240363636A1

公开(公告)日：2024-10-31

申请号：US18768702

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming isolation regions extending into a semiconductor substrate, forming a plurality of semiconductor fins protruding higher than top surfaces of the isolation regions, forming a gate stack on the plurality of semiconductor fins, forming a gate spacer on a sidewall of the gate stack, and recessing the plurality of semiconductor fins to form a plurality of recesses on a side of the gate stack. The plurality of recesses extend to a level lower than top surfaces of the isolation regions. Epitaxy processes are performed to grow an epitaxy region, wherein the epitaxy region fills the plurality of recesses.