公开(公告)号：US09881652B2

公开(公告)日：2018-01-30

申请号：US15391744

申请日：2016-12-27

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John W. Poulton

IPC: H04B15/00 ,  G11C5/14 ,  G06F11/07

CPC classification number: G11C5/144 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/0793 ,  G06F13/4072 ,  G11C5/145 ,  H04L1/203 ,  H04L25/0264 ,  H04L25/08

Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

公开(公告)号：US09870283B2

公开(公告)日：2018-01-16

申请号：US14864500

申请日：2015-09-24

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Craig E. Hampel

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07 ,  G06F11/16 ,  H03M13/09

CPC classification number: G06F11/1004 ,  G06F11/0703 ,  G06F11/073 ,  G06F11/1679 ,  H03M13/09

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation

公开(公告)号：US20180006852A1

公开(公告)日：2018-01-04

申请号：US15652059

申请日：2017-07-17

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Fred F. Chen ,  Andrew Ho ,  Ramin Farjad-Rad ,  John W. Poulton ,  Kevin S. Donnelly ,  Brian S. Leibowitz

IPC: H04L27/01 ,  H04L7/033 ,  H04L1/00 ,  H04W52/20 ,  H04L25/03 ,  H04L25/497 ,  H04W52/22 ,  H04L7/00 ,  H04L25/02

CPC classification number: H04L27/01 ,  H04L1/0026 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/0337 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/03057 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/497 ,  H04L2025/03503 ,  H04W52/20 ,  H04W52/225 ,  Y02D70/00

Abstract: A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

公开(公告)号：US20180006737A1

公开(公告)日：2018-01-04

申请号：US15652047

申请日：2017-07-17

Applicant: Rambus Inc.

Inventor： Jun Kim ,  Wayne S. Richardson ,  Glenn Chiu

IPC: H04B17/11 ,  H04L5/14 ,  H04L25/03

CPC classification number: H04B17/11 ,  H04L5/1438 ,  H04L25/03343 ,  H04L2025/03802

Abstract: A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.

公开(公告)号：US09860089B2

公开(公告)日：2018-01-02

申请号：US15208332

申请日：2016-07-12

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Brian S. Leibowitz ,  Jade M. Kizer ,  Thomas H. Greer ,  Akash Bansal

IPC: H04L25/03 ,  H04B1/12

CPC classification number: H04L25/03159 ,  H04B1/123 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03636

Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

公开(公告)号：US09859899B2

公开(公告)日：2018-01-02

申请号：US15009485

申请日：2016-01-28

Applicant: Rambus Inc.

Inventor： Marko Aleksić ,  Brian S. Leibowitz

IPC: H03B5/08 ,  H03B5/18 ,  H03L1/00 ,  H03L7/24 ,  H03K3/03 ,  H03L7/083

CPC classification number: H03L1/00 ,  H03K3/0315 ,  H03L7/083 ,  H03L7/24

Abstract: A variable injection-strength injection-locked oscillator (ILO) is described. The variable injection-strength ILO can output an output clock signal based on an input clock signal. The variable injection-strength ILO can pause, restart, slow down, or speed up the output clock signal synchronously with respect to the input clock signal in response to receiving power mode information. Specifically, the variable injection-strength ILO can be operated under relatively strong injection when the input clock signal is paused, restarted, slowed down, or sped up.

公开(公告)号：US20170372768A1

公开(公告)日：2017-12-28

申请号：US15616209

申请日：2017-06-07

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G11C11/4076 ,  G06F1/08 ,  G11C11/4096 ,  G11C11/408 ,  G06F1/32 ,  G11C11/4072 ,  G06F1/04 ,  G11C7/20 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4074

CPC classification number: G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4096 ,  Y02D10/128 ,  Y02D50/20

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US09851900B2

公开(公告)日：2017-12-26

申请号：US15629173

申请日：2017-06-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G06F3/06 ,  G11C8/12 ,  G06F12/06

CPC classification number: G06F3/0604 ,  G06F3/0635 ,  G06F3/0673 ,  G06F12/06 ,  G06F2212/1048 ,  G11C8/12 ,  G11C2207/107

Abstract: A multiple memory rank selection method and system assigns, based at least in part on decoding an assignment signal in a second command/address signal, a first terminal of a memory device to receive a first command/address signal and a second terminal of the memory device to receive the second command/address signal or assigns the first terminal of the memory device to receive the second command/address signal and the second terminal of the memory device to receive the first command/address signal. The multiple memory selection method and system decodes a selection signal encoded in the first command/address signal and enables the memory device based at least in part on the assignment signal and the selection signal.

公开(公告)号：US09841806B1

公开(公告)日：2017-12-12

申请号：US14706886

申请日：2015-05-07

Applicant: Rambus Inc.

Inventor： Chris Haywood

IPC: G06F1/32 ,  G11C14/00 ,  G11C7/10

CPC classification number: G06F1/3275 ,  G11C5/04 ,  G11C5/14 ,  G11C7/1072 ,  G11C14/0009

Abstract: A memory load sharing system and method therefor. This system can include a platform VRM (Voltage Regulator Module) coupled to a memory channel with the platform VRM having a platform voltage input. One or more first memory modules can coupled to the platform VRM through the memory channel. Each of the first memory modules includes one or more plane connectors and a module connector, as well as a memory module VRM coupled to a module load sharing diode that is coupled to the one or more plane connectors of that first memory module. The platform VRM is coupled to a first platform load sharing diode that is coupled the plane connectors of each of the first memory modules. This platform is configured to support load sharing between the first memory modules and to provide a predetermined amount of power to each of the memory modules.

公开(公告)号：US20170351627A1

公开(公告)日：2017-12-07

申请号：US15533630

申请日：2015-10-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Kenneth L. Wright

IPC: G06F13/28 ,  G06F13/16

CPC classification number: G06F13/287 ,  G06F13/16 ,  G06F2213/28 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045

Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.