公开(公告)号：US09472520B2

公开(公告)日：2016-10-18

申请号：US13590332

申请日：2012-08-21

Applicant: Virendra R. Jadhav ,  Krystyna W. Semkow ,  Kamalesh K. Srivastava ,  Brian R. Sundlof

Inventor： Virendra R. Jadhav ,  Krystyna W. Semkow ,  Kamalesh K. Srivastava ,  Brian R. Sundlof

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/562 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/13655 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13684 ,  H01L2224/16235 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2924/384 ,  Y10T156/10 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.

Abstract translation: 提供了一种多层柱及其制造方法。 多层柱用作芯片和基板之间的互连。 支柱具有至少一个低强度，高延展性变形区域，其被配置为吸收在芯片组装和热偏移期间施加的力。

公开(公告)号：US20130016479A1

公开(公告)日：2013-01-17

申请号：US13553887

申请日：2012-07-20

Applicant: Gareth Hougham ,  Paul A. Lauro ,  Brian R. Sundlof ,  Jeffrey D. Gelorme

Inventor： Gareth Hougham ,  Paul A. Lauro ,  Brian R. Sundlof ,  Jeffrey D. Gelorme

IPC: C09K5/00 ,  B32B37/26 ,  H05K7/20

CPC classification number: H01L23/3733 ,  B82Y30/00 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/40 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  Y10S977/788 ,  Y10T156/10 ,  Y10T428/24994 ,  H01L2224/0401

Abstract: The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite.

Abstract translation: 本发明一般涉及用于集成电路的导热膏，特别是但不限于石墨的自取向微孔板。

公开(公告)号：US20120312447A1

公开(公告)日：2012-12-13

申请号：US13590332

申请日：2012-08-21

Applicant: Virendra R. JADHAV ,  Krystyna W. SEMKOW ,  Kamalesh K. SRIVASTAVA ,  Brian R. SUNDLOF

Inventor： Virendra R. JADHAV ,  Krystyna W. SEMKOW ,  Kamalesh K. SRIVASTAVA ,  Brian R. SUNDLOF

IPC: B05D5/12 ,  B32B37/14 ,  B23K31/02 ,  B32B37/12

CPC classification number: H01L24/13 ,  H01L23/562 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/13655 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13684 ,  H01L2224/16235 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2924/384 ,  Y10T156/10 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.

Abstract translation: 提供了一种多层柱及其制造方法。 多层柱用作芯片和基板之间的互连。 支柱具有至少一个低强度，高延展性变形区域，其构造成吸收在芯片组装和热偏移期间施加的力。

公开(公告)号：US20120202343A1

公开(公告)日：2012-08-09

申请号：US13448500

申请日：2012-04-17

Applicant: Luc Bélanger ,  Srinivasa S.N. Reddy ,  Brian R. Sundlof

Inventor： Luc Bélanger ,  Srinivasa S.N. Reddy ,  Brian R. Sundlof

IPC: H01L21/44

CPC classification number: H01L24/13 ,  C22C19/03 ,  C23C14/025 ,  C23C14/165 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/0554 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A metallic adhesion layer is formed on a last level metal plate exposed in an opening of a passivation layer. A Ni—Cu alloy in which the weight percentage of Ni is from about 50% to about 70% is deposited by sputtering onto the metallic adhesion layer to form an underbump metallic layer. Optionally, a wetting layer comprising Cu or Au may be deposited by sputtering. A C4 ball is applied to a surface of the underbump metallic layer comprising the Ni—Cu alloy or the wetting layer for C4 processing. The sputter deposition of the Ni—Cu alloy offers economic advantages relative to known methods in the art since the Ni—Cu alloy in the composition of the present invention is non-magnetic and easy to sputter, and the consumption of the inventive Ni—Cu alloy is limited during C4 processing.

Abstract translation: 在暴露在钝化层的开口中的最后一级金属板上形成金属粘附层。 通过溅射将Ni的重量百分比为约50％至约70％的Ni-Cu合金沉积到金属粘合层上以形成下凸块金属层。 任选地，可以通过溅射沉积包含Cu或Au的润湿层。 将C4球施加到包含Ni-Cu合金或用于C4加工的润湿层的底部基底金属层的表面上。 Ni-Cu合金的溅射沉积相对于本领域已知的方法提供经济优势，因为本发明组合物中的Ni-Cu合金是非磁性的并且易于溅射，并且本发明的Ni-Cu C4加工时合金有限。

公开(公告)号：US20100207056A1

公开(公告)日：2010-08-19

申请号：US12772774

申请日：2010-05-03

Applicant: Gareth Hougham ,  Paul A. Lauro ,  Brian R. Sundlof ,  Jeffrey D. Gelorme

Inventor： Gareth Hougham ,  Paul A. Lauro ,  Brian R. Sundlof ,  Jeffrey D. Gelorme

IPC: C09K5/00

CPC classification number: H01L23/3733 ,  B82Y30/00 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/40 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  Y10S977/788 ,  Y10T156/10 ,  Y10T428/24994 ,  H01L2224/0401

Abstract: The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite.

Abstract translation: 本发明一般涉及用于集成电路的导热膏，特别是但不限于石墨的自取向微孔板。

公开(公告)号：US20090267228A1

公开(公告)日：2009-10-29

申请号：US12111510

申请日：2008-04-29

Applicant: Charles L. Arvin ,  Carla A. Bailey ,  Harry D. Cox ,  Hua Gan ,  Hsichang Liu ,  Arthur G. Merryman ,  Vall F. McClean ,  Srinivasa S. N. Reddy ,  Brian R. Sundlof

Inventor： Charles L. Arvin ,  Carla A. Bailey ,  Harry D. Cox ,  Hua Gan ,  Hsichang Liu ,  Arthur G. Merryman ,  Vall F. McClean ,  Srinivasa S. N. Reddy ,  Brian R. Sundlof

IPC: H01L23/52 ,  H01L21/44

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/03462 ,  H01L2224/03472 ,  H01L2224/03831 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05017 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05564 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: One embodiment of the present invention is directed to an under bump metallurgy material. The under bump metallurgy material of this embodiment includes an adhesion layer and a conduction layer formed on top of the adhesion layer. The under bump metallurgy material of this embodiment also includes a barrier layer plated on top of the conduction layer and a sacrificial layer plated on top of the barrier layer. The conduction layer of this embodiment includes a trench formed therein, the trench contacting a portion of the barrier layer and blocking a path of intermetallic formation between the conduction layer and the sacrificial layer.

Abstract translation: 本发明的一个实施例涉及一种凸块下金属材料。 本实施方式的凸块状冶金材料包括粘合层和形成在粘合层顶部的导电层。 该实施例的凸块下冶金材料还包括电镀在导电层顶部上的阻挡层和镀在阻挡层顶部上的牺牲层。 该实施例的导电层包括在其中形成的沟槽，沟槽接触势垒层的一部分并且阻挡导电层和牺牲层之间的金属间形成路径。

公开(公告)号：US20090140423A1

公开(公告)日：2009-06-04

申请号：US11947070

申请日：2007-11-29

Applicant: Luc Belanger ,  Srinivasa S.N. Reddy ,  Da-Yuan Shih ,  Brian R. Sundlof

Inventor： Luc Belanger ,  Srinivasa S.N. Reddy ,  Da-Yuan Shih ,  Brian R. Sundlof

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/13 ,  C22C19/007 ,  C22C19/03 ,  C23C14/025 ,  C23C14/165 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/0554 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13006 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A a metallic adhesion layer is formed on a last level metal plate exposed in an opening of a passivation layer. A Ni—Ti alloy in which the weight percentage of Ti is from about 6.5% to about 30% is deposited by sputtering onto the metallic adhesion layer to form an underbump metallic layer. A wetting layer comprising Cu or Ag or Au is deposited on top of Ni—Ti layer by sputtering. A C4 ball is applied to a surface of the wetting layer for C4 processing. The sputter deposition of the Ni—Ti alloy offers economic and performance advantages relative to known methods in the art since the Ni—Ti alloy in the composition of the present invention is non-magnetic and easy to sputter, and the consumption of the inventive Ni—Ti alloy is limited during C4 processing. Also, Sn in the solder reacts uniformly with both Ni and Ti and the consumption of Ni—Ti by Sn solder is less than that for pure Ni.

Abstract translation: 在暴露在钝化层的开口中的最后一级金属板上形成金属粘合层。 其中Ti的重量百分数为约6.5％至约30％的Ni-Ti合金通过溅射沉积到金属粘合层上以形成底部金属层。 通过溅射将包含Cu或Ag或Au的润湿层沉积在Ni-Ti层的顶部上。 将C4球施加到用于C4加工的润湿层的表面。 Ni-Ti合金的溅射沉积相对于本领域已知的方法提供经济和性能优点，因为本发明组合物中的Ni-Ti合金是非磁性的并且易于溅射，并且本发明的Ni -Ti合金在C4加工过程中受到限制。 此外，焊料中的Sn与Ni和Ti均匀地反应，Sn焊料的Ni-Ti的消耗小于纯Ni的消耗。

公开(公告)号：US20090134016A1

公开(公告)日：2009-05-28

申请号：US11946231

申请日：2007-11-28

Applicant: Luc Belanger ,  Srinivasa S.N. Reddy ,  Brian R. Sundlof

Inventor： Luc Belanger ,  Srinivasa S.N. Reddy ,  Brian R. Sundlof

IPC: C23C14/00

CPC classification number: H01L24/13 ,  C22C19/03 ,  C23C14/025 ,  C23C14/165 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/0554 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A metallic adhesion layer is formed on a last level metal plate exposed in an opening of a passivation layer. A Ni—Cu alloy in which the weight percentage of Ni is from about 50% to about 70% is deposited by sputtering onto the metallic adhesion layer to form an underbump metallic layer. Optionally, a wetting layer comprising Cu or Au may be deposited by sputtering. A C4 ball is applied to a surface of the underbump metallic layer comprising the Ni—Cu alloy or the wetting layer for C4 processing. The sputter deposition of the Ni—Cu alloy offers economic advantages relative to known methods in the art since the Ni—Cu alloy in the composition of the present invention is non-magnetic and easy to sputter, and the consumption of the inventive Ni—Cu alloy is limited during C4 processing.

Abstract translation: 在暴露在钝化层的开口中的最后一级金属板上形成金属粘附层。 通过溅射将Ni的重量百分比为约50％至约70％的Ni-Cu合金沉积到金属粘合层上以形成下凸块金属层。 任选地，可以通过溅射沉积包含Cu或Au的润湿层。 将C4球施加到包含Ni-Cu合金或用于C4加工的润湿层的底部基底金属层的表面上。 Ni-Cu合金的溅射沉积相对于本领域已知的方法提供经济优势，因为本发明组合物中的Ni-Cu合金是非磁性的并且易于溅射，并且本发明的Ni-Cu C4加工时合金有限。

公开(公告)号：US20090095502A1

公开(公告)日：2009-04-16

申请号：US11870583

申请日：2007-10-11

Applicant: VIRENDRA R. JADHAV ,  KRYSTYNA W. SEMKOW ,  KAMALESH K. SRIVASTAVA ,  BRIAN R. SUNDLOF

Inventor： VIRENDRA R. JADHAV ,  KRYSTYNA W. SEMKOW ,  KAMALESH K. SRIVASTAVA ,  BRIAN R. SUNDLOF

IPC: H01B5/02 ,  H01L21/60

CPC classification number: H01L24/13 ,  H01L23/562 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/13655 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13684 ,  H01L2224/16235 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2924/384 ,  Y10T156/10 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions

Abstract translation: 提供了一种多层柱及其制造方法。 多层柱用作芯片和基板之间的互连。 支柱具有至少一个低强度，高延展性变形区域，其被配置为吸收在芯片组装和热偏移期间施加的力