公开(公告)号：US20060158829A1

公开(公告)日：2006-07-20

申请号：US11335411

申请日：2006-01-19

Applicant: Dae-jin Kwon ,  Seok-jun Won ,  Weon-hong Kim ,  Yong-kuk Jeong ,  Min-woo Song ,  Jung-min Park

Inventor： Dae-jin Kwon ,  Seok-jun Won ,  Weon-hong Kim ,  Yong-kuk Jeong ,  Min-woo Song ,  Jung-min Park

IPC: H01G4/20

CPC classification number: H01G4/10 ,  H01G4/20

Abstract: Multi-layered dielectric films which can improve the performance characteristics of a microelectronic device are provided as well as methods of manufacturing the same. The multi-layered dielectric film includes a single component oxide layer made of a single component oxide, and composite components oxide layers made of a composite components oxide including two or more different components formed along either side of the single component oxide layer without a layered structure.

公开(公告)号：US20060156980A1

公开(公告)日：2006-07-20

申请号：US11321491

申请日：2005-12-29

Applicant: Seok-jun Won ,  Yong-min Yoo ,  Dae-youn Kim ,  Young-hoon Kim ,  Dae-jin Kwon ,  Weon-hong Kim

Inventor： Seok-jun Won ,  Yong-min Yoo ,  Dae-youn Kim ,  Young-hoon Kim ,  Dae-jin Kwon ,  Weon-hong Kim

IPC: C23C16/00 ,  C03C25/68 ,  H01L21/306 ,  H01L21/302 ,  H01L21/31

CPC classification number: C23C16/45544 ,  C23C16/0272 ,  C23C16/403 ,  C23C16/405 ,  C23C16/4402 ,  C23C16/45561 ,  C23C16/45574 ,  H01L21/00 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/0262 ,  H01L21/28556 ,  H01L21/28562 ,  Y10T137/0318

Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.

公开(公告)号：US07563672B2

公开(公告)日：2009-07-21

申请号：US11593670

申请日：2006-11-07

Applicant: Dae-Jin Kwon ,  Jung-Min Park ,  Seok-Jun Won ,  Min-Woo Song ,  Weon-hong Kim ,  Ju-youn Kim

Inventor： Dae-Jin Kwon ,  Jung-Min Park ,  Seok-Jun Won ,  Min-Woo Song ,  Weon-hong Kim ,  Ju-youn Kim

IPC: H01L21/8242

CPC classification number: H01L27/016 ,  H01L23/5223 ,  H01L28/75 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

Abstract: Integrated circuit devices including metal-insulator-metal (MIM) capacitors are provided. The MIM capacitors may include an upper electrode having first and second layers. The first layer of the upper electrode includes a physical vapor deposition (PVD) upper electrode and the second layer of the upper electrode includes an ionized PVD (IPVD) upper electrode on the PVD upper electrode. Related methods are also provided.

Abstract translation: 提供了包括金属 - 绝缘体 - 金属（MIM）电容器的集成电路器件。 MIM电容器可以包括具有第一层和第二层的上电极。 上电极的第一层包括物理气相沉积（PVD）上电极，并且上电极的第二层在PVD上电极上包括离子化的PVD（IPVD）上电极。 还提供了相关方法。

公开(公告)号：US20080211059A1

公开(公告)日：2008-09-04

申请号：US12013290

申请日：2008-01-11

Applicant: Dae-Jin KWON ,  Woo-Sik KIM ,  Maeda Shigenobu ,  Seung-Hwan LEE ,  Sung-Rey WI ,  Wang-Xiao Quan ,  Hyun-Min CHOI

Inventor： Dae-Jin KWON ,  Woo-Sik KIM ,  Maeda Shigenobu ,  Seung-Hwan LEE ,  Sung-Rey WI ,  Wang-Xiao Quan ,  Hyun-Min CHOI

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a fuse transistor for fuse programming and a fuse block connected to the fuse transistor, wherein the fuse block comprises a fuse line and a heat spreading structure connected to the fuse line. The electrical fuse employs the heat spreading structure connected to the fuse line to prevent a rupture of the electrical fuse such that heat, which is generated in the fuse line during a blowing of the fuse line, is spread throughout the heat spreading structure. Thus, a sensing margin of the electrical fuse can be secured and a deterioration of devices adjacent to the electrical fuse by heat generated in the electrical fuse can be prevented.

Abstract translation: 半导体器件包括用于熔丝编程的熔丝晶体管和连接到熔丝晶体管的熔丝块，其中熔丝块包括熔丝线和连接到熔丝线的散热结构。 电熔丝采用连接到熔丝线的散热结构，以防止电熔丝断裂，使得在熔断丝熔化期间在熔丝线中产生的热量散布在整个散热结构中。 因此，可以确保电熔丝的感测余量，并且可以防止在电熔丝中产生的热量与电熔丝相邻的器件的劣化。

公开(公告)号：US07407897B2

公开(公告)日：2008-08-05

申请号：US11173624

申请日：2005-07-01

Applicant: Seok-jun Won ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

Inventor： Seok-jun Won ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

IPC: H01L29/00

CPC classification number: H01L28/40 ,  H01L28/65 ,  Y10S438/957

Abstract: In a capacitor of an analog semiconductor device having a multi-layer dielectric film and a method of manufacturing the same, the multi-layer dielectric film can be readily manufactured, has weak reactivity with corresponding electrodes and offers excellent leakage current characteristics. In order to obtain these advantages, a lower dielectric film having a negative quadratic VCC, an intermediate dielectric film having a positive quadratic VCC, and an upper dielectric film having a negative quadratic VCC are sequentially formed between a lower electrode and an upper electrode. The lower dielectric film and the upper dielectric film may be composed of SiO2. The intermediate dielectric film may be composed of HFO2.

Abstract translation: 在具有多层电介质膜的模拟半导体器件的电容器及其制造方法中，可以容易地制造多层电介质膜，与相应的电极具有弱反应性并提供优异的漏电流特性。 为了获得这些优点，在​​下电极和上电极之间顺序地形成具有负二次VCC的下电介质膜，具有正二次VCC的中间电介质膜和具有负二次VCC的上电介质膜。 下电介质膜和上电介质膜可以由SiO 2组成。 中间电介质膜可以由HFO 2 N 2构成。

公开(公告)号：US07095460B2

公开(公告)日：2006-08-22

申请号：US10083261

申请日：2002-02-25

Applicant: Joon-Hoo Choi ,  Wan-Shick Hong ,  Dae-Jin Kwon ,  Kwan-Wook Jung ,  Sang-Gab Kim ,  Kyu-Ha Jung

Inventor： Joon-Hoo Choi ,  Wan-Shick Hong ,  Dae-Jin Kwon ,  Kwan-Wook Jung ,  Sang-Gab Kim ,  Kyu-Ha Jung

IPC: G02F1/136

CPC classification number: H01L29/66765 ,  G02F1/136227 ,  G02F2001/133357 ,  G02F2001/136236 ,  H01L27/12 ,  H01L29/458 ,  H01L29/4908

Abstract: A thin film transistor array substrate is provided. The substrate includes an insulating substrate, a first signal line formed on the insulating substrate, a first insulating layer formed on the first signal line, a second signal line formed on the first insulating layer while crossing over the first signal line, a thin film transistor connected to the first and the second signal lines, a second insulating layer formed on the thin film transistor, the second insulating layer having dielectric constant about 4.0 or less, and the second insulating layer having a first contact hole exposing a predetermined electrode of the thin film transistor, and a first pixel electrode formed on the second insulating layer while being connected to the predetermined electrode of the thin film transistor through the first contact hole.

公开(公告)号：US20060124987A1

公开(公告)日：2006-06-15

申请号：US11345776

申请日：2006-02-01

Applicant: Seok-Jun Won ,  Myong-geun Yoon ,  Yong-Kuk Jeong ,  Dae-jin Kwon

Inventor： Seok-Jun Won ,  Myong-geun Yoon ,  Yong-Kuk Jeong ,  Dae-jin Kwon

IPC: H01L29/94

CPC classification number: H01L21/022 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02337 ,  H01L21/3141 ,  H01L21/3143 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/56 ,  H01L28/65

Abstract: Provided is a capacitor of a semiconductor device. The capacitor includes a capacitor lower electrode disposed on a semiconductor substrate. A first dielectric layer comprising aluminum oxide (Al2O3) is disposed on the capacitor lower electrode. A second dielectric layer comprising a material having a higher dielectric constant than that of aluminum oxide is disposed on the first dielectric layer. A third dielectric layer comprising aluminum oxide is disposed on the second dielectric layer. A capacitor upper electrode is disposed on the third dielectric layer. The capacitor of the present invention can improve electrical properties. Thus, power consumption can be reduced and capacitance per unit area is high enough to achieve high integration.

Abstract translation: 提供一种半导体器件的电容器。 电容器包括设置在半导体衬底上的电容器下电极。 包含氧化铝（Al 2 O 3 3）的第一电介质层设置在电容器下电极上。 包括具有比氧化铝介电常数更高的介电常数的材料的第二电介质层设置在第一电介质层上。 包含氧化铝的第三电介质层设置在第二电介质层上。 电容器上电极设置在第三电介质层上。 本发明的电容器可以改善电气性能。 因此，可以降低功耗，并且每单位面积的电容足够高以实现高集成度。

公开(公告)号：US20060006449A1

公开(公告)日：2006-01-12

申请号：US11174954

申请日：2005-07-05

Applicant: Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

Inventor： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

IPC: H01L27/108

CPC classification number: H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/02197 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L27/0805 ,  H01L28/56 ,  H01L28/65

Abstract: In semiconductor integrated circuit devices having a hybrid dielectric layer and methods of fabricating the same, the hybrid dielectric layer includes a lower dielectric layer, an intermediate dielectric layer and an upper dielectric layer which are sequentially stacked. The lower dielectric layer contains hafnium (Hf) or zirconium (Zr). The upper dielectric layer also contains Hf or Zr. The intermediate dielectric layer is formed of a material layer having a voltage dependent capacitance variation lower than that of the lower dielectric layer.

Abstract translation: 在具有混合电介质层的半导体集成电路器件及其制造方法中，混合电介质层包括依次层叠的下部电介质层，中间电介质层和上部电介质层。 下介电层含有铪（Hf）或锆（Zr）。 上部介电层也含有Hf或Zr。 中间电介质层由具有相对于下电介质层的电压相关电容变化的材料层形成。

公开(公告)号：US20050152094A1

公开(公告)日：2005-07-14

申请号：US11032150

申请日：2005-01-11

Applicant: Yong-kuk Jeong ,  Jung-Hyoung Lee ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim ,  Min-woo Song

Inventor： Yong-kuk Jeong ,  Jung-Hyoung Lee ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim ,  Min-woo Song

IPC: H01L27/108 ,  H01G4/10 ,  H01G4/20 ,  H01L21/02 ,  H01L27/08 ,  H01G4/28

CPC classification number: H01L21/02172 ,  H01G4/10 ,  H01G4/20 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31645 ,  H01L27/0805 ,  H01L28/56 ,  H01L28/65

Abstract: In a capacitor, and a method of fabricating the same, the capacitor includes a lower electrode, a dielectric layer on the lower electrode, and an upper electrode on the dielectric layer, wherein the dielectric layer includes a lower dielectric region contacting the lower electrode, an upper dielectric region contacting the upper electrode, and at least one middle dielectric region between the lower dielectric region and the upper dielectric region, the at least one middle dielectric region having a less crystalline region than both the lower dielectric region and the upper dielectric region.

Abstract translation: 在电容器及其制造方法中，电容器包括下电极，下电极上的电介质层和电介质层上的上电极，其中介电层包括与下电极接触的下电介质区域， 与上部电极接触的上部电介质区域，以及位于下部电介质区域和上部电介质区域之间的至少一个中间电介质区域，所述至少一个中间电介质区域具有比下部电介质区域和上部电介质区域更小的结晶区域 。

公开(公告)号：US20050130427A1

公开(公告)日：2005-06-16

申请号：US11007884

申请日：2004-12-09

Applicant: Seok-Jun Won ,  Weon-Hong Kim ,  Dae-Jin Kwon

Inventor： Seok-Jun Won ,  Weon-Hong Kim ,  Dae-Jin Kwon

IPC: H01L21/304 ,  C23C16/44 ,  H01L21/302 ,  H01L21/314 ,  H01L21/316 ,  H01L21/461

CPC classification number: C23C16/4404 ,  C23C16/4405 ,  H01L21/3141 ,  H01L21/31637

Abstract: There is provided a method of forming a thin film for providing improved fabrication productivity. The method includes introducing a semiconductor substrate into a process chamber. A process thin film is formed on the semiconductor substrate, in which a chamber coating layer is formed on inner walls of the process chamber while the process thin film is formed. The semiconductor substrate is removed from the process chamber. A stress relief layer is formed on the chamber coating layer. After all of the above operations are repeatedly performed at least one time, an in-situ cleaning is performed on the chamber coating layer and the stress relief layer, which are alternately formed in stack on the inner walls of the process chamber.

Abstract translation: 提供了形成薄膜以提高制造生产率的方法。 该方法包括将半导体衬底引入到处理室中。 在半导体衬底上形成工艺薄膜，其中在形成工艺薄膜的同时，在处理室的内壁上形成腔室涂层。 将半导体衬底从处理室中取出。 在室涂层上形成应力消除层。 在上述操作全部反复进行至少一次之后，对处理室内壁交替形成的室涂层和应力消除层进行原位清洗。