公开(公告)号：US06449156B1

公开(公告)日：2002-09-10

申请号：US09952303

申请日：2001-09-12

Applicant: Seong-Chan Han ,  Dong-Woo Shin ,  Dong-Chun Lee ,  Wang-Jae Lee

Inventor： Seong-Chan Han ,  Dong-Woo Shin ,  Dong-Chun Lee ,  Wang-Jae Lee

IPC: H05K720

CPC classification number: G11C5/04

Abstract: A novel heat sink structure for being mounted to a module board to which semiconductor chips are attached and for dissipating or spreading heat generated from the semiconductor chips is disclosed. The heat sink comprises a heat sink base, and a coupling means for coupling the heat sink base to the module board. The coupling means passes through the heat sink base. The coupling means includes integrally formed upper and lower body portions, an orifice formed at least through the lower body portion, and a flanged base formed integral with the lower body portion. The flanged base fixes the coupling means to the heat sink base. The outer dimension of the upper body portion is smaller than the inner dimension of the lower body portion. As a result, many heat sinks can be stacked stably.

Abstract translation: 公开了一种新颖的散热器结构，用于安装到模块板，半导体芯片被附着到模块板上，并用于散发或扩散从半导体芯片产生的热量。 散热器包括散热器基座和用于将散热器基座耦合到模块板的耦合装置。 联接装置通过散热器底座。 联接装置包括一体形成的上主体部分和至少穿过下主体部分的孔口，以及与下主体部分一体形成的凸缘基部。 带凸缘的底座将联接装置固定在散热器底座上。 上身部的外部尺寸小于下主体部的内部尺寸。 结果，许多散热器可以稳定堆叠。

公开(公告)号：US08556725B2

公开(公告)日：2013-10-15

申请号：US13242711

申请日：2011-09-23

Applicant: Chang-Sik Cho ,  Dong-Chun Lee ,  Su-Young Bae ,  Hang-Kee Kim ,  Kang-Min Sohn ,  Chang-Joon Park

Inventor： Chang-Sik Cho ,  Dong-Chun Lee ,  Su-Young Bae ,  Hang-Kee Kim ,  Kang-Min Sohn ,  Chang-Joon Park

IPC: G07F17/32

CPC classification number: A63F13/358 ,  A63F2300/534 ,  A63F2300/535

Abstract: Disclosed herein is a scenario-based load testing apparatus and method. The scenario-based load testing apparatus includes a packet analysis unit, a scenario creation unit, and a load generation unit. The packet analysis unit creates a virtual map and game grammar by capturing and analyzing packets sent between a server and a client. The scenario creation unit creates a scenario of a virtual user on the virtual map. The load generation unit generates a load by creating packet data corresponding to the virtual user in compliance with the game grammar and the scenario.

Abstract translation: 这里公开了基于情景的负载测试装置和方法。 基于情况的负载测试装置包括分组分析单元，场景创建单元和负载生成单元。 分组分析单元通过捕获和分析在服务器和客户端之间发送的分组来创建虚拟映射和游戏语法。 场景创建单元在虚拟地图上创建虚拟用户的场景。 负载生成单元通过根据游戏语法和场景创建与虚拟用户对应的分组数据来生成负载。

公开(公告)号：US08385080B2

公开(公告)日：2013-02-26

申请号：US13006692

申请日：2011-01-14

Applicant: Jung-Hoon Kim ,  Seong-Chan Han ,  Dong-Chun Lee ,  Jae-Hoon Choi ,  Sun-Kyu Hwang

Inventor： Jung-Hoon Kim ,  Seong-Chan Han ,  Dong-Chun Lee ,  Jae-Hoon Choi ,  Sun-Kyu Hwang

IPC: H05K7/00

CPC classification number: H05K7/00

Abstract: A semiconductor module, a socket for the same, and a semiconductor module/socket assembly are disclosed. The semiconductor module includes a printed circuit board including a plurality of semiconductor devices, a plurality of insulating layers and a plurality of metal layers, the plurality of insulating layers and the plurality of metal layers are alternately stacked. Exposed portions of the metal layers are exposed to the outside of the semiconductor module at a first and a second ends of the printed circuit board. The first end and the second end are at opposite ends of the printed circuit board.

Abstract translation: 公开了半导体模块，用于其的插座和半导体模块/插座组件。 半导体模块包括具有多个半导体器件，多个绝缘层和多个金属层的印刷电路板，多个绝缘层和多个金属层交替堆叠。 金属层的露出部分在印刷电路板的第一和第二端处暴露于半导体模块的外部。 第一端和第二端位于印刷电路板的相对端。

公开(公告)号：US07902664B2

公开(公告)日：2011-03-08

申请号：US11878084

申请日：2007-07-20

Applicant: Hyo-jae Bang ,  Dong-chun Lee ,  Seong-chan Han ,  Kyung-du Kim ,  Sun-kyu Hwang

Inventor： Hyo-jae Bang ,  Dong-chun Lee ,  Seong-chan Han ,  Kyung-du Kim ,  Sun-kyu Hwang

IPC: H01L23/34

CPC classification number: H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/0231 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: Example embodiments relate to a semiconductor package. The semiconductor package may include a mounting substrate, a semiconductor chip mounted to the mounting substrate, at least one passive component passing therethrough and mounted to the mounting substrate, and a cover covering the mounting substrate, the semiconductor chip and the at least one passive component.

Abstract translation: 示例实施例涉及半导体封装。 半导体封装可以包括安装基板，安装到安装基板的半导体芯片，穿过其中并安装到安装基板的至少一个无源部件，以及覆盖安装基板，半导体芯片和至少一个无源部件 。

公开(公告)号：US07728966B2

公开(公告)日：2010-06-01

申请号：US11423677

申请日：2006-06-12

Applicant: Jong-An Kim ,  Dong-Chun Lee ,  Chung-Sam Jun ,  Ik-Chul Kim ,  Sang-Hee Kim

Inventor： Jong-An Kim ,  Dong-Chun Lee ,  Chung-Sam Jun ,  Ik-Chul Kim ,  Sang-Hee Kim

IPC: G01N21/00

CPC classification number: G01N21/9501 ,  G01N2021/8825

Abstract: An optical inspection tool used to detect surface defects of a substrate include a chuck for holding a substrate and a lens unit disposed over the chuck. The lens unit includes at least a pair of oblique beam paths therein, wherein light penetrating the beam paths travels without angular deflection. The beam paths take the form of spaces formed through the lens unit, or flat portions formed on a lens within the lens unit. A camera is installed on the lens unit, and the camera converts light passing through the lens unit into an image. Methods of detecting surface defects of the substrate using the inspection tool are also provided.

Abstract translation: 用于检测基板的表面缺陷的光学检查工具包括用于保持基板的卡盘和设置在卡盘上方的透镜单元。 透镜单元在其中包括至少一对倾斜光束路径，其中穿透光束路径的光行进而没有角度偏转。 光束路径采取通过透镜单元形成的空间的形式，或形成在透镜单元内的透镜上的平坦部分。 相机安装在镜头单元上，相机将通过镜头单元的光转换为图像。 还提供了使用检查工具检测基板的表面缺陷的方法。

公开(公告)号：US20100105201A1

公开(公告)日：2010-04-29

申请号：US12650093

申请日：2009-12-30

Applicant: Hyo-Jae Bang ,  Heui-Seog Kim ,  Dong-Chun Lee ,  Seong-Chan Han ,  Jung-Hyeon Kim

Inventor： Hyo-Jae Bang ,  Heui-Seog Kim ,  Dong-Chun Lee ,  Seong-Chan Han ,  Jung-Hyeon Kim

IPC: H01L21/60

CPC classification number: H05K3/303 ,  H05K2201/0305 ,  H05K2201/09781 ,  H05K2201/10689 ,  H05K2201/2036 ,  Y02P70/613

Abstract: A semiconductor device includes a semiconductor package, a circuit board and an interval maintaining member. The semiconductor package has a body and a lead protruded from the body. The circuit board has a first land electrically connected to the lead. The interval maintaining member is interposed between the circuit board and the body. The interval maintaining member maintains an interval between the lead and the first land. Thus, an interval between the lead and the land is uniformly maintained, so that a thermal and/or mechanical reliability of the semiconductor device is improved.

Abstract translation: 半导体器件包括半导体封装，电路板和间隔保持元件。 半导体封装具有从主体突出的主体和引线。 电路板具有与引线电连接的第一焊盘。 间隔保持构件插入在电路板和主体之间。 间隔保持构件保持引线与第一焊盘之间的间隔。 因此，均匀地保持引线和焊盘之间的间隔，从而提高了半导体器件的热和/或机械可靠性。

公开(公告)号：US07498248B2

公开(公告)日：2009-03-03

申请号：US11590072

申请日：2006-10-31

Applicant: Jung-Taek Lim ,  Dong-Chun Lee ,  Young-Jee Yoon ,  Sung-Hong Park

Inventor： Jung-Taek Lim ,  Dong-Chun Lee ,  Young-Jee Yoon ,  Sung-Hong Park

IPC: H01L21/3205

CPC classification number: G03F7/70633

Abstract: In the methods of compensating for an alignment error during fabrication of structures on semiconductor substrates, a conductive pattern structure is formed at a first position on a first semiconductor substrate. The conductive pattern structure includes a grid of first and second conductive patterns arranged as columns and intersecting rows with openings bounded therebetween. A first conductive contact structure overlaps the conductive pattern structure, and includes a plurality of spaced apart conductive contacts arranged as a grid of rows and columns that can be tilted at a non-zero angle relative to the grid of the conductive pattern structure. A determination is made as to whether the first conductive contact structure is electrically connected to the conductive pattern structure. A second conductive contact structure is formed at a position on a second semiconductor substrate that is determined in response to the determination of whether the first conductive contact structure is electrically connected to the conductive pattern structure.

Abstract translation: 在半导体衬底上的结构制造期间补偿对准误差的方法中，在第一半导体衬底上的第一位置处形成导电图案结构。 导电图案结构包括布置成列和相交行的第一和第二导电图案的格栅，其间具有开口。 第一导电接触结构与导电图案结构重叠，并且包括布置成可以相对于导电图案结构的格栅非零角度倾斜的行和列格栅的多个间隔开的导电接点。 确定第一导电接触结构是否电连接到导电图案结构。 第二导电接触结构形成在第二半导体衬底上的响应于第一导电接触结构是否电连接到导电图案结构的确定而确定的位置。

公开(公告)号：US20090016022A1

公开(公告)日：2009-01-15

申请号：US12172133

申请日：2008-07-11

Applicant: Hun HAN ,  Dong-Chun LEE ,  Hyo-Jae BANG

Inventor： Hun HAN ,  Dong-Chun LEE ,  Hyo-Jae BANG

IPC: H05K7/20

CPC classification number: H05K1/189 ,  G11C5/04 ,  H05K1/0272 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/064 ,  H05K2201/09445 ,  H05K2201/10159 ,  H05K2203/1572

Abstract: A semiconductor module includes a base plate, a circuit substrate coupled to a side face of the base plate, a first semiconductor package mounted on the circuit substrate and a radiation channel portion inside the base plate. The radiation channel portion includes at least one heat pipe containing a working fluid. The at least one heat pipe containing the working fluid is configured to transfer heat generated by the first semiconductor package. Thus, the radiation channel portion may provide an efficient and reliable semiconductor module having improved heat transfer and radiation performance.

Abstract translation: 半导体模块包括基板，耦合到基板的侧面的电路基板，安装在电路基板上的第一半导体封装和基板内部的辐射通道部分。 辐射通道部分包括至少一个含有工作流体的热管。 含有工作流体的至少一个热管构造成传递由第一半导体封装产生的热量。 因此，辐射通道部分可以提供具有改进的热传递和辐射性能的有效且可靠的半导体模块。

公开(公告)号：US20080157389A1

公开(公告)日：2008-07-03

申请号：US11968035

申请日：2007-12-31

Applicant: Chang-Yong Park ,  Kwang-Ho Chun ,  Dong-Chun Lee ,  Yong-Hyun Kim

Inventor： Chang-Yong Park ,  Kwang-Ho Chun ,  Dong-Chun Lee ,  Yong-Hyun Kim

IPC: H01L23/48 ,  H05K7/02

CPC classification number: H05K1/111 ,  H01L2924/0002 ,  H05K3/3452 ,  H05K2201/0367 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09845 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: Provided are a semiconductor package and a module printed circuit board (PCB) for mounting the same. Each of the semiconductor package and the module PCB includes a substrate, a first-type pad structure disposed in a first region of the substrate, and a second-type pad structure disposed in a second region of the package substrate. The first-type pad includes a first conductive pad disposed on the package substrate and a first insulating layer coated on the package substrate. The first insulating layer has a first opening by which a portion of a sidewall of the first conductive pad is exposed, and partially covers the first conductive pad. The second-type pad includes a second insulating layer coated on the package substrate to have a second opening and a second conductive pad disposed on the package substrate in the second opening to have an exposed sidewall. In this structure, the semiconductor package and the module PCB can have an excellent resistance to physical and thermal stresses to enhance structural reliability.

Abstract translation: 提供了用于安装它的半导体封装和模块印刷电路板（PCB）。 半导体封装和模块PCB中的每一个包括衬底，设置在衬底的第一区域中的第一类型衬垫结构以及设置在封装衬底的第二区域中的第二类型衬垫结构。 第一型焊盘包括设置在封装衬底上的第一导电焊盘和涂覆在封装衬底上的第一绝缘层。 第一绝缘层具有第一开口，通过该第一开口，第一导电焊盘的侧壁的一部分被暴露，并且部分覆盖第一导电焊盘。 第二类型衬垫包括涂覆在封装衬底上以具有第二开口的第二绝缘层和设置在第二开口中的封装衬底上的具有暴露侧壁的第二导电焊盘。 在这种结构中，半导体封装和模块PCB可以具有优异的耐物理和热应力，以增强结构可靠性。

公开(公告)号：US20080136580A1

公开(公告)日：2008-06-12

申请号：US11947422

申请日：2007-11-29

Applicant: Hyo-Jae BANG ,  Dong-Chun LEE ,  Seong-Chan HAN ,  Jung-Hyeon KIM ,  Hyun-Seok CHOI

Inventor： Hyo-Jae BANG ,  Dong-Chun LEE ,  Seong-Chan HAN ,  Jung-Hyeon KIM ,  Hyun-Seok CHOI

IPC: H01C1/01

CPC classification number: H01C1/144 ,  H01C1/01 ,  H01C7/18 ,  H05K3/3436 ,  H05K3/3442 ,  H05K2201/09172 ,  H05K2201/10045 ,  Y02P70/613

Abstract: Provided are a chip network resistor contacting a printed circuit board (PCB) through solder balls and a semiconductor module having the chip network resistor. The chip network resistor includes: a body formed of an insulating material; a resistor formed on the body; external electrodes connected to the resistor and disposed on a lower surface of the body so as to have solder ball pad shapes; and conductive balls adhered on the external electrodes.

Abstract translation: 提供了通过焊球与印刷电路板（PCB）接触的芯片网络电阻器和具有芯片网络电阻器的半导体模块。 芯片网络电阻器包括：由绝缘材料形成的主体; 形成在体上的电阻; 外部电极连接到电阻器并且设置在主体的下表面上以具有焊球形状; 并且导电球附着在外部电极上。