公开(公告)号：US07638440B2

公开(公告)日：2009-12-29

申请号：US10799146

申请日：2004-03-12

Applicant: Yuxiang May Wang ,  Sudha S. R. Rathi ,  Michael Chiu Kwan ,  Hichem M'Saad

Inventor： Yuxiang May Wang ,  Sudha S. R. Rathi ,  Michael Chiu Kwan ,  Hichem M'Saad

IPC: H01L21/31 ,  H01L21/469

CPC classification number: G03F7/094 ,  G03F7/091 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76829 ,  H01L21/7684

Abstract: Methods are provided for depositing amorphous carbon materials. In one aspect, the invention provides a method for processing a substrate including forming a dielectric material layer on a surface of the substrate, depositing an amorphous carbon layer on the dielectric material layer by introducing a processing gas comprises one or more hydrocarbon compounds and an argon carrier gas, and generating a plasma of the processing gas by applying power from a dual-frequency RF source, etching the amorphous carbon layer to form a patterned amorphous carbon layer, and etching feature definitions in the dielectric material layer corresponding to the patterned amorphous carbon layer. The amorphous carbon layer may act as an etch stop, an anti-reflective coating, or both.

Abstract translation: 提供了沉积无定形碳材料的方法。 一方面，本发明提供了一种处理衬底的方法，包括在衬底的表面上形成介电材料层，通过引入包含一种或多种烃化合物和氩气的处理气体在电介质材料层上沉积无定形碳层 并且通过从双频RF源施加电力来产生处理气体的等离子体，蚀刻无定形碳层以形成图案化的非晶碳层，并且在对应于图案化无定形碳的电介质材料层中蚀刻特征定义 层。 无定形碳层可用作蚀刻停止层，抗反射涂层或两者。

公开(公告)号：US07601651B2

公开(公告)日：2009-10-13

申请号：US11668911

申请日：2007-01-30

Applicant: Mihaela Balseanu ,  Meiyee Shek ,  Li-Qun Xia ,  Hichem M'Saad

Inventor： Mihaela Balseanu ,  Meiyee Shek ,  Li-Qun Xia ,  Hichem M'Saad

IPC: H01L21/31

CPC classification number: H01L21/76834 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/76829 ,  H01L21/76831

Abstract: A method of forming a layer on a substrate in a chamber, wherein the substrate has at least one formed feature across its surface, is provided. The method includes exposing the substrate to a silicon-containing precursor in the presence of a plasma to deposit a layer, treating the deposited layer with a plasma, and repeating the exposing and treating until a desired thickness of the layer is obtained. The plasma may be generated from an oxygen-containing gas.

Abstract translation: 提供了一种在室中的衬底上形成层的方法，其中衬底在其表面上具有至少一个形成的特征。 该方法包括在存在等离子体的情况下将衬底暴露于含硅前体以沉积一层，用等离子体处理沉积层，并重复曝光和处理，直到获得所需层厚。 等离子体可以由含氧气体产生。

公开(公告)号：US07572337B2

公开(公告)日：2009-08-11

申请号：US11131010

申请日：2005-05-16

Applicant: Juan Carlos Rocha-Alvarez ,  Ganesh Balasubramanian ,  Tom K. Cho ,  Deenesh Padhi ,  Thomas Nowak ,  Bok Hoen Kim ,  Hichem M'Saad ,  Daemian Raj

Inventor： Juan Carlos Rocha-Alvarez ,  Ganesh Balasubramanian ,  Tom K. Cho ,  Deenesh Padhi ,  Thomas Nowak ,  Bok Hoen Kim ,  Hichem M'Saad ,  Daemian Raj

IPC: C23C16/455 ,  C23F1/00 ,  H01L21/306 ,  C23C16/06 ,  C23C16/22

CPC classification number: C23C16/45574 ,  C23C16/4405 ,  C23C16/45565 ,  H01J37/3244 ,  H01J37/32449

Abstract: Apparatus and methods for distributing gases into a processing chamber are disclosed. In one embodiment, the apparatus includes a gas distribution plate having a plurality of apertures disposed therethrough and a blocker plate having both a plurality of apertures disposed therethrough and a plurality of feed through passageways disposed therein. A first gas pathway delivers a first gas through the plurality of apertures in the blocker plate and the gas distribution plate. A bypass gas pathway delivers a second gas through the plurality of feed through passageways in the blocker plate and to areas around the blocker plate prior to the second gas passing through the gas distribution plate.

Abstract translation: 公开了将气体分配到处理室中的装置和方法。 在一个实施例中，该装置包括一个气体分配板，该气体分配板具有穿过其中的多个孔，以及一个阻挡板，其具有设置在其间的多个孔和设置在其中的多个进给通道。 第一气体通道通过阻挡板和气体分配板中的多个孔传送第一气体。 旁路气体通道在第二气体通过气体分配板之前，通过多个进料通过阻挡板中的通道和阻塞板周围的区域输送第二气体。

公开(公告)号：US07566655B2

公开(公告)日：2009-07-28

申请号：US11398436

申请日：2006-04-05

Applicant: Mihaela Balseanu ,  Jia Lee ,  Mei-Yee Shek ,  Amir Al-Bayati ,  Li-Qun Xia ,  Hichem M'Saad

Inventor： Mihaela Balseanu ,  Jia Lee ,  Mei-Yee Shek ,  Amir Al-Bayati ,  Li-Qun Xia ,  Hichem M'Saad

IPC: H01L21/44

CPC classification number: H01L29/7843 ,  C23C16/345 ,  C23C16/56 ,  H01L21/28044 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4925 ,  H01L29/66545 ,  H01L29/66583

Abstract: A process flow integration scheme employs one or more techniques to control stress in a semiconductor device formed thereby. In accordance with one embodiment, cumulative stress contributed by RTP of a nitride spacer and polysilicon gate, and subsequent deposition of a high stress etch stop layer, enhance strain and improve device performance. Germanium may be deposited or implanted into the gate structure in order to facilitate stress control.

Abstract translation: 工艺流程集成方案采用一种或多种技术来控制由此形成的半导体器件中的应力。 根据一个实施例，由氮化物间隔物和多晶硅栅极的RTP贡献的累积应力以及随后沉积高应力蚀刻停止层，增强应变并提高器件性能。 可以将锗沉积或植入栅极结构中以便于应力控制。

公开(公告)号：US20090162259A1

公开(公告)日：2009-06-25

申请号：US12393851

申请日：2009-02-26

Applicant: Thomas Nowak ,  Juan Carlos Rocha-Alvarez ,  Andrzej Kaszuba ,  Scott A. Hendrickson ,  Dustin W. Ho ,  Sanjeev Baluja ,  Tom Cho ,  Josephine Chang ,  Hichem M'saad

Inventor： Thomas Nowak ,  Juan Carlos Rocha-Alvarez ,  Andrzej Kaszuba ,  Scott A. Hendrickson ,  Dustin W. Ho ,  Sanjeev Baluja ,  Tom Cho ,  Josephine Chang ,  Hichem M'saad

IPC: B01J19/08

CPC classification number: B05D3/067 ,  B05D3/0209 ,  B05D3/0493 ,  H01L21/31058

Abstract: An ultraviolet (UV) cure chamber enables curing a dielectric material disposed on a substrate and in situ cleaning thereof. A tandem process chamber provides two separate and adjacent process regions defined by a body covered with a lid having windows aligned respectively above each process region. One or more UV sources per process region that are covered by housings coupled to the lid emit UV light directed through the windows onto substrates located within the process regions. The UV sources can be an array of light emitting diodes or bulbs utilizing a source such as microwave or radio frequency. The UV light can be pulsed during a cure process. Using oxygen radical/ozone generated remotely and/or in-situ accomplishes cleaning of the chamber. Use of lamp arrays, relative motion of the substrate and lamp head, and real-time modification of lamp reflector shape and/or position can enhance uniformity of substrate illumination.

Abstract translation: 紫外线（UV）固化室可固化设置在基底上的电介质材料并进行原位清洁。 串联处理室提供由覆盖有盖的主体限定的两个单独的和相邻的过程区域，所述盖子具有分别位于每个处理区域上方的窗口。 每个处理区域的一个或多个UV源被耦合到盖的壳体覆盖，将通过窗口的UV光发射到位于处理区域内的衬底上。 UV源可以是利用诸如微波或射频之类的源的发光二极管或灯泡阵列。 紫外光可以在固化过程中被脉冲。 使用远程生成的氧自由基/臭氧和/或原位实现清洁室。 灯阵列的使用，基板和灯头的相对运动以及灯反射器形状和/或位置的实时修改可以增强基板照明的均匀性。

公开(公告)号：US20090137132A1

公开(公告)日：2009-05-28

申请号：US12365669

申请日：2009-02-04

Applicant: Ritwik Bhatia ,  Li-Qun Xia ,  Chad Peterson ,  Hichem M'Saad

Inventor： Ritwik Bhatia ,  Li-Qun Xia ,  Chad Peterson ,  Hichem M'Saad

IPC: H01L21/31

CPC classification number: H01L21/0332 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3185 ,  H01L21/76825 ,  H01L21/76829

Abstract: Methods for forming silicon nitride hard masks are provided. The silicon nitride hard masks include carbon-doped silicon nitride layers and undoped silicon nitride layers. Carbon-doped silicon nitride layers that are deposited from a mixture comprising a carbon source compound, a silicon source compound, and a nitrogen source in the presence of RF power are provided. Also provided are methods of UV post-treating silicon nitride layers to provide silicon nitride hard masks. The carbon-doped silicon nitride layers and UV post-treated silicon nitride layers have desirable wet etch rates and dry etch rates for hard mask layers.

Abstract translation: 提供了形成氮化硅硬掩模的方法。 氮化硅硬掩模包括碳掺杂的氮化硅层和未掺杂的氮化硅层。 提供了在RF功率存在下由包含碳源化合物，硅源化合物和氮源的混合物沉积的碳掺杂氮化硅层。 还提供了UV后处理氮化硅层以提供氮化硅硬掩模的方法。 碳掺杂的氮化硅层和UV后处理的氮化硅层对于硬掩模层具有期望的湿蚀刻速率和干蚀刻速率。

公开(公告)号：US20090093132A1

公开(公告)日：2009-04-09

申请号：US11869416

申请日：2007-10-09

Applicant: HUIWEN XU ,  Yijun Liu ,  Li-Qun Xia ,  Derek R. Witty ,  Hichem M'Saad

Inventor： HUIWEN XU ,  Yijun Liu ,  Li-Qun Xia ,  Derek R. Witty ,  Hichem M'Saad

IPC: H01L21/31

CPC classification number: H01L21/02205 ,  C23C16/22 ,  C23C16/505 ,  H01L21/02112 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/3121 ,  H01L21/3148 ,  H01L21/3185

Abstract: The present invention generally provides a method for forming a dielectric barrier with lowered dielectric constant, improved etching resistivity and good barrier property. One embodiment provides a method for processing a semiconductor substrate comprising flowing a precursor to a processing chamber, wherein the precursor comprises silicon-carbon bonds and carbon-carbon bonds, and generating a low density plasma of the precursor in the processing chamber to form a dielectric barrier film having carbon-carbon bonds on the semiconductor substrate, wherein the at least a portion of carbon-carbon bonds in the precursor is preserved in the low density plasma and incorporated in the dielectric barrier film.

Abstract translation: 本发明通常提供一种形成具有降低的介电常数，改进的蚀刻电阻率和良好的阻挡性能的介电阻挡层的方法。 一个实施例提供了一种用于处理半导体衬底的方法，包括将前体流入处理室，其中前体包含硅 - 碳键和碳 - 碳键，并在处理室中产生前体的低密度等离子体以形成电介质 在半导体衬底上具有碳 - 碳键的阻挡膜，其中前体中的至少一部分碳 - 碳键保存在低密度等离子体中并且并入介电阻挡膜中。

公开(公告)号：US20080254233A1

公开(公告)日：2008-10-16

申请号：US11733531

申请日：2007-04-10

Applicant: KWANGDUK DOUGLAS LEE ,  Matthew Spuller ,  Martin Jay Seamons ,  Wendy H. Yeh ,  Bok Hoen Kim ,  Mohamad Ayoub ,  Amir Al-Bayati ,  Derek R. Witty ,  Hichem M'Saad

Inventor： KWANGDUK DOUGLAS LEE ,  Matthew Spuller ,  Martin Jay Seamons ,  Wendy H. Yeh ,  Bok Hoen Kim ,  Mohamad Ayoub ,  Amir Al-Bayati ,  Derek R. Witty ,  Hichem M'Saad

IPC: C23C14/28

CPC classification number: C23C16/26 ,  C23C16/52

Abstract: Methods of depositing amorphous carbon films on substrates are provided herein. The methods reduce or prevent plasma-induced charge damage to the substrates from the deposition of the amorphous carbon films. In one aspect, an initiation layer of amorphous carbon is deposited at a low RF power level and/or at a low hydrocarbon compound/inert gas flow rate ratio before a bulk layer of amorphous carbon is deposited. After the deposition of the initiation layer, the RF power, hydrocarbon flow rate, and inert gas flow rate may be ramped to final values for the deposition of the bulk layer, wherein the RF power ramp rate is typically greater than the ramp rates of the hydrocarbon compound and of the inert gas. In another aspect, a method of minimizing plasma-induced charge damage includes depositing a seasoning layer on one or more interior surfaces of a chamber before the deposition of the amorphous carbon film on a substrate therein or coating the interior surfaces with an oxide or dielectric layer during manufacturing.

Abstract translation: 本文提供了在基片上沉积非晶碳膜的方法。 该方法从无定形碳膜的沉积中减少或防止等离子体对基板的电荷损伤。 在一个方面，在堆积无定形碳沉积层之前，以低RF功率水平和/或低烃化合物/惰性气体流速比沉积无定形碳的起始层。 在起始层的沉积之后，RF功率，烃流速和惰性气体流速可以斜坡化到用于沉积体层的最终值，其中RF功率斜坡率通常大于 烃化合物和惰性气体。 在另一方面，一种使等离子体感应的电荷损伤最小化的方法包括在将非晶碳膜沉积在基底上之前，在腔室的一个或多个内表面上沉积调味层，或者用氧化物或介电层涂覆内表面 在制造过程中。

公开(公告)号：US07371427B2

公开(公告)日：2008-05-13

申请号：US10442579

申请日：2003-05-20

Applicant: Nagarajan Rajagopalan ,  Meiyee Shek ,  Kegang Huang ,  Bok Hoen Kim ,  Hichem M'saad ,  Thomas Nowak

Inventor： Nagarajan Rajagopalan ,  Meiyee Shek ,  Kegang Huang ,  Bok Hoen Kim ,  Hichem M'saad ,  Thomas Nowak

IPC: B08B9/00 ,  B05D7/22

CPC classification number: H01L21/7684 ,  C23C16/4404 ,  C23G5/00 ,  H01L21/3212 ,  H01L21/76828 ,  H01L21/76838

Abstract: Unwanted hillocks arising in copper layers due to formation of overlying barrier layers may be significantly reduced by optimizing various process parameters, alone or in combination. A first set of process parameters may be controlled to pre-condition the processing chamber in which the barrier layer is deposited. A second set of process parameters may be controlled to minimize energy to which a copper layer is exposed during removal of CuO prior to barrier deposition. A third set of process parameters may be controlled to minimize the thermal budget after removal of the copper oxide.

Abstract translation: 由于形成覆盖势垒层而在铜层中产生的不希望的小丘可以通过单独或组合优化各种工艺参数而显着降低。 可以控制第一组工艺参数以对其中沉积阻挡层的处理室进行预处理。 可以控制第二组工艺参数，以在阻挡层沉积之前最小化去除CuO期间铜层暴露的能量。 可以控制第三组工艺参数以最小化除去氧化铜后的热预算。

公开(公告)号：US20080075888A1

公开(公告)日：2008-03-27

申请号：US11876680

申请日：2007-10-22

Applicant: Nagarajan Rajagopalan ,  Meiyee Shek ,  Kegang Huang ,  Bok Heon Kim ,  Hichem M'saad ,  Thomas Nowak

Inventor： Nagarajan Rajagopalan ,  Meiyee Shek ,  Kegang Huang ,  Bok Heon Kim ,  Hichem M'saad ,  Thomas Nowak

IPC: H05H1/24

CPC classification number: H01L21/7684 ,  C23C16/4404 ,  C23G5/00 ,  H01L21/3212 ,  H01L21/76828 ,  H01L21/76838

Abstract: Unwanted hillocks arising in copper layers due to formation of overlying barrier layers may be significantly reduced by optimizing various process parameters, alone or in combination. A first set of process parameters may be controlled to pre-condition the processing chamber in which the barrier layer is deposited. A second set of process parameters may be controlled to minimize energy to which a copper layer is exposed during removal of CuO prior to barrier deposition. A third set of process parameters may be controlled to minimize the thermal budget after removal of the copper oxide.

Abstract translation: 由于形成覆盖势垒层而在铜层中产生的不希望的小丘可以通过单独或组合优化各种工艺参数而显着降低。 可以控制第一组工艺参数以对其中沉积阻挡层的处理室进行预处理。 可以控制第二组工艺参数，以在阻挡层沉积之前最小化去除CuO期间铜层暴露的能量。 可以控制第三组工艺参数以最小化除去氧化铜后的热预算。