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    Memory system and timing control method of the same
    31.
    发明申请
    Memory system and timing control method of the same 有权
    内存系统和时序控制方法相同

    公开(公告)号：US20050010741A1

    公开(公告)日：2005-01-13

    申请号：US10886926

    申请日：2004-07-08

    Applicant: Jung-Bae Lee ,  Hoe-Ju Chung

    Inventor： Jung-Bae Lee ,  Hoe-Ju Chung

    IPC: G11C7/00 ,  G06F12/02 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22

    CPC classification number: G06F13/1689 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C2207/2254

    Abstract: A memory system includes at least one memory module, each of which has a pattern data generating circuit for generating a pattern data, which has a plurality of memories to which a command signal is commonly applied and corresponding data is applied respectively; and a memory controller for respectively applying the command signal and the corresponding data to the plurality of memories, applying a pattern data generating command to the memory module during a timing control operation, calculating time differences among data of reaching each of the plurality of memories using the pattern data outputted from each of the memories and receiving and outputting data using the calculated data reaching time difference. Therefore, a stable data transmission is achieved between the memory controller and the memories.

    Abstract translation: 存储器系统包括至少一个存储器模块，每个存储器模块具有用于产生模式数据的模式数据产生电路，该模式数据具有共同应用命令信号的多个存储器，并且分别应用相应的数据; 以及存储器控制器，用于分别将命令信号和相应的数据应用于多个存储器，在定时控制操作期间向存储器模块应用模式数据产生命令，使用以下方式计算到达多个存储器中的每一个的数据之间的时间差： 从每个存储器输出的图案数据，并使用计算出的数据到达时间差来接收和输出数据。 因此，在存储器控制器和存储器之间实现稳定的数据传输。

    PAD arrangement in semiconductor memory device and method of driving semiconductor device
    32.
    发明授权
    PAD arrangement in semiconductor memory device and method of driving semiconductor device 有权
    半导体存储器件中的PAD布置和半导体器件的驱动方法

    公开(公告)号：US06806582B2

    公开(公告)日：2004-10-19

    申请号：US10054700

    申请日：2002-01-17

    Applicant: Mee-Hyun Ahn ,  Jung-Bae Lee

    Inventor： Mee-Hyun Ahn ,  Jung-Bae Lee

    IPC: H01L2348

    CPC classification number: H01L23/50 ,  G11C5/025 ,  G11C2207/105 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor memory device comprising control pads and input/output I/O pads capable of reducing the data path for reading and writing data in a cell array, and a method for driving the semiconductor memory device are included. The semiconductor memory device comprises a plurality of memory banks arranged at a cell region of a memory chip, and a plurality of control pads and a plurality of I/O pads, separately arranged from each other at the memory chip, for reading/writing data from/in the memory banks, wherein the plurality of control pads and I/O pads are dispersed at the peripheral region between adjacent memory banks and at the outer portions of the memory banks.

    Abstract translation: 一种半导体存储器件，包括能够减少用于在单元阵列中读取和写入数据的数据路径的控制焊盘和输入/输出I / O焊盘，以及用于驱动半导体存储器件的方法。 半导体存储器件包括布置在存储器芯片的单元区域的多个存储器组，以及多个控制焊盘和多个I / O焊盘，这些控制焊盘和多个I / O焊盘在存储芯片处彼此分开布置，用于读/写数据 来自/在存储体中，其中多个控制焊盘和I / O焊盘分散在相邻存储体之间的周边区域和存储体的外部。

    Semiconductor memory device for reducing chip size
    33.
    发明授权
    Semiconductor memory device for reducing chip size 有权
    用于减小芯片尺寸的半导体存储器件

    公开(公告)号：US06804163B2

    公开(公告)日：2004-10-12

    申请号：US10305986

    申请日：2002-11-29

    Applicant: Yun-sang Lee ,  Jung-bae Lee

    Inventor： Yun-sang Lee ,  Jung-bae Lee

    IPC: G11C800

    CPC classification number: G11C7/12 ,  G11C5/025 ,  G11C7/06 ,  G11C7/10

    Abstract: A semiconductor memory device that minimizes chip area is provided. The semiconductor memory device includes local input/output (I/O) lines, global I/O lines, and a memory core that is coupled between a bit line and a complementary bit line. The memory core includes a memory cell array, a bit line equalizer circuit, a PMOS sense amplifier (S/A), a PMOS S/A driving circuit for driving the PMOS S/A, a transmission gate circuit, an NMOS S/A, and an NMOS S/A driving circuit for driving the NMOS S/A. First and second transistors for connecting the local I/O lines to the global I/O lines are installed between adjacent bit lines. The PMOS S/A driving circuit, which is a first driving transistor, and the NMOS S/A driving circuit, which is a second driving transistor, are also installed between adjacent bit lines. Because the semiconductor memory device arranges a PMOS S/A driving circuit, an NMOS S/A driving circuit, and a gating circuit for connecting local I/O lines to global I/O lines, between adjacent bit lines, the chip area is reduced.

    Abstract translation: 提供了最小化芯片面积的半导体存储器件。 半导体存储器件包括本地输入/输出（I / O）线，全局I / O线和耦合在位线和互补位线之间的存储器核。 存储器芯包括存储单元阵列，位线均衡器电路，PMOS读出放大器（S / A），用于驱动PMOS S / A的PMOS S / A驱动电路，传输门电路，NMOS S / A 以及用于驱动NMOS S / A的NMOS S / A驱动电路。 用于将本地I / O线连接到全局I / O线的第一和第二晶体管安装在相邻位线之间。 作为第一驱动晶体管的PMOS S / A驱动电路和作为第二驱动晶体管的NMOS S / A驱动电路也安装在相邻位线之间。 由于半导体存储器件在相邻位线之间配置PMOS S / A驱动电路，NMOS S / A驱动电路和用于将本地I / O线连接到全局I / O线的选通电路，芯片面积减小 。

    Semiconductor memory device having a fixed CAS latency and/or burst length
    34.
    发明授权
    Semiconductor memory device having a fixed CAS latency and/or burst length 失效
    具有固定CAS延迟和/或突发长度的半导体存储器件

    公开(公告)号：US06564287B1

    公开(公告)日：2003-05-13

    申请号：US09655643

    申请日：2000-09-05

    Applicant: Jung-Bae Lee

    Inventor： Jung-Bae Lee

    IPC: G06F1300

    CPC classification number: G11C29/12015 ,  G11C7/1018 ,  G11C7/1045 ,  G11C8/18 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/50012

    Abstract: A semiconductor memory device is provided in which a burst length and/or a column address strobe (CAS) latency may be fixed. The semiconductor memory device, which may be an SDRAM (synchronous dynamic random access memory) device, includes a memory cell array, a burst address generation circuit to generate a burst address and a burst length detection signal, a mode setting register for setting a CAS latency and/or a burst length using an address, a pipeline circuit to delay and output data read from the memory cell array. The semiconductor memory device also includes a latency enable control signal generation circuit to generate a latency enable control signal in response to a read command or signal and the burst length detection signal, and a data output circuit to output data being output from the pipeline circuit in response to the latency enable control signal. Therefore, a circuit configuration is simplified and a test time is reduced, by fixing latency and/or burst length.

    Abstract translation: 提供半导体存储器件，其中可以固定突发长度和/或列地址选通（CAS）等待时间。 可以是SDRAM（同步动态随机存取存储器）装置的半导体存储器件包括存储单元阵列，用于产生脉冲串地址和脉冲串长度检测信号的突发地址产生电路，用于设置CAS的模式设置寄存器 延迟和/或突发长度，使用地址，流水线电路来延迟和输出从存储器单元阵列读取的数据。 半导体存储器件还包括等待时间使能控制信号产生电路，以响应于读命令或信号以及突发长度检测信号产生等待时间使能控制信号，以及数据输出电路，用于输出从管线电路输出的数据 响应延迟启用控制信号。 因此，通过固定延迟和/或突发长度，简化了电路配置并减少了测试时间。

    Input buffer circuits with input signal boost capability and methods of operation thereof
    35.
    发明授权
    Input buffer circuits with input signal boost capability and methods of operation thereof 失效
    具有输入信号提升能力的输入缓冲电路及其操作方法

    公开(公告)号：US06414517B1

    公开(公告)日：2002-07-02

    申请号：US09685266

    申请日：2000-10-10

    Applicant: Kyu-hyoun Kim ,  Jung-bae Lee

    Inventor： Kyu-hyoun Kim ,  Jung-bae Lee

    IPC: H03K19094

    CPC classification number: H04L25/028 ,  H04L25/0272

    Abstract: An input buffer includes an amplifier circuit, such as a differential amplifier circuit, inverting amplifier circuit or pull-up/pull-down amplifier circuit. A momentary boost circuit is coupled to an input buffer input terminal, an input terminal of the amplifier circuit, and an output terminal of the amplifier circuit, and is operative to generate a boosted input signal at the input terminal of the amplifier circuit from an input signal at an input buffer input terminal for an interval that is terminated responsive to an output signal at the output terminal of the amplifier circuit. The momentary boost circuit may include a detector circuit coupled to the output terminal of the amplifier circuit and operative to generate a control signal responsive to a transition of the output signal, and a boost circuit, coupled between the input buffer input terminal and the input terminal of the amplifier circuit and operatively associated with the detector circuit, that receives the input signal at the input buffer input terminal and generates the boosted input signal at the input terminal of the amplifier circuit from the received input signal responsive to the control signal. For example, the boost circuit may include a capacitor coupled between the input buffer input terminal and the input terminal of the amplifier circuit, and a switch that couples and decouples the input terminal of the amplifier circuit to a reference voltage source responsive to the control signal. The detector circuit may be operative to generate a pulse responsive to a transition of the output signal, and the switch may be operative to couple the input terminal of the amplifier circuit to the reference voltage source responsive to the pulse.

    Abstract translation: 输入缓冲器包括诸如差分放大器电路，反相放大器电路或上拉/下拉放大器电路的放大器电路。 瞬时升压电路耦合到输入缓冲器输入端子，放大器电路的输入端子和放大器电路的输出端子，并且可操作以从放大器电路的输入端在输入端产生升压输入信号 在输入缓冲器输入端子处，响应于在放大器电路的输出端子处的输出信号而终止的间隔的信号。 瞬时升压电路可以包括耦合到放大器电路的输出端的检测器电路，并且可操作以响应于输出信号的转变而产生控制信号，以及耦合在输入缓冲器输入端和输入端之间的升压电路 并且与检测器电路可操作地相关联，其在输入缓冲器输入端子处接收输入信号，并且响应于控制信号从所接收的输入信号在放大器电路的输入端产生升压的输入信号。 例如，升压电路可以包括耦合在输入缓冲器输入端子和放大器电路的输入端子之间的电容器，以及响应于控制信号将放大器电路的输入端子耦合到参考电压源的开关 。 检测器电路可操作以响应于输出信号的转变而产生脉冲，并且开关可以用于响应于脉冲将放大器电路的输入端耦合到参考电压源。

    Integrated circuit memory devices having data selection circuits therein which are compatible with single and dual rate mode operation and methods of operating same
    36.
    发明授权
    Integrated circuit memory devices having data selection circuits therein which are compatible with single and dual rate mode operation and methods of operating same 有权
    其中具有与单速率和双速率模式操作兼容的数据选择电路的集成电路存储器件及其操作方法

    公开(公告)号：US6151271A

    公开(公告)日：2000-11-21

    申请号：US235471

    申请日：1999-01-22

    Applicant: Jung-bae Lee

    Inventor： Jung-bae Lee

    IPC: G11C11/407 ,  G11C7/10 ,  G11C8/12 ,  G11C8/18 ,  G11C11/401 ,  G11C8/00

    CPC classification number: G11C7/1045 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  G11C8/18

    Abstract: Integrated circuit memory devices include first and second memory banks, first and second local data lines electrically coupled to the first and second memory banks, respectively, and a multiplexer having first and second inputs electrically coupled to first and second data bus lines, respectively. A data selection circuit is also provided which routes data from the first and second local data lines to the first and second data bus lines, respectively, when a selection control signal is in a first logic state and routes data from the second and first local data lines to the first and second data bus lines, respectively, when a selection control signal is in a. second logic state opposite the first logic state. A control signal generator is also provided. This control signal generator generates the selection control signal in the first and second logic states when a first address in a string of burst addresses is even and odd, respectively.

    Abstract translation: 集成电路存储器件包括第一和第二存储体，分别电耦合到第一和第二存储体的第一和第二本地数据线以及分别具有电耦合到第一和第二数据总线的第一和第二输入的多路复用器。 还提供了一种数据选择电路，当选择控制信号处于第一逻辑状态并将来自第二和第一本地数据的数据进行路由时，分别将数据从第一和第二本地数据线路路由到第一和第二数据总线 当选择控制信号为a时，分别连接到第一和第二数据总线。 第二逻辑状态与第一逻辑状态相反。 还提供控制信号发生器。 当脉冲串地址串中的第一地址分别为偶数和奇数时，该控制信号发生器产生第一和第二逻辑状态中的选择控制信号。

    Current-mode bidirectional input/output buffer
    37.
    发明授权
    Current-mode bidirectional input/output buffer 失效
    电流模式双向输入/输出缓冲器

    公开(公告)号：US6075384A

    公开(公告)日：2000-06-13

    申请号：US49739

    申请日：1998-03-27

    Applicant: Jae-Yoon Sim ,  Hong-Joon Park ,  Soo-In Cho ,  Jung-Bae Lee

    Inventor： Jae-Yoon Sim ,  Hong-Joon Park ,  Soo-In Cho ,  Jung-Bae Lee

    IPC: H03K17/00 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0185

    CPC classification number: H03K19/018592

    Abstract: A bidirectional input/output buffer operates in a current mode to increase the data transfer rate between devices connected by a bidirectional transmission line. The buffer includes an output current source for generating an output current responsive to a data output signal. The output current is combined with an output current indicative of a data input signal received from another device over a transmission line, thereby forming a mixed current signal. The data input signal is restored from the mixed signal by a restoring circuit that compares the mixed signal to a reference current that depends on the value of the data output signal. The restoring circuit includes a current mirror and a reference current source that generates a reference current in response to the data output signal. To provide additional performance, an embodiment of a bidirectional input/output buffer utilizes a switchless structure having two comparators that compare the mixed signal to two different reference signals, thereby generating two comparison signals. A selector circuit selects one of the two comparison signals as the restored data input signal responsive to the data output signal.

    Abstract translation: 双向输入/输出缓冲器以当前模式工作，以增加通过双向传输线连接的设备之间的数据传输速率。 缓冲器包括用于响应于数据输出信号产生输出电流的输出电流源。 输出电流与表示通过传输线从另一设备接收的数据输入信号的输出电流组合，从而形成混合电流信号。 数据输入信号通过将混合信号与取决于数据输出信号的值的参考电流进行比较的恢复电路从混合信号中恢复。 恢复电路包括响应于数据输出信号产生参考电流的电流镜和参考电流源。 为了提供额外的性能，双向输入/输出缓冲器的实施例利用具有两个比较器的无开关结构，其将混合信号与两个不同的参考信号进行比较，从而产生两个比较信号。 选择器电路根据数据输出信号选择两个比较信号中的一个作为恢复的数据输入信号。

    Circuit for generating an internal clock for data output buffers in a synchronous DRAM devices
    38.
    发明授权
    Circuit for generating an internal clock for data output buffers in a synchronous DRAM devices 失效
    用于在同步DRAM器件中产生数据输出缓冲器的内部时钟的电路

    公开(公告)号：US5844438A

    公开(公告)日：1998-12-01

    申请号：US771198

    申请日：1996-12-20

    Applicant: Jung-Bae Lee

    Inventor： Jung-Bae Lee

    IPC: G11C11/409 ,  G06F12/00 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4093 ,  H03K5/13 ,  H03K5/156 ,  H03K21/00

    CPC classification number: H03K5/156 ,  G11C7/22 ,  H03K5/13

    Abstract: An internal clock generating circuit for data output buffers of a synchronous DRAM device, which produces an internal clock with reference to either the positive edge or the negative edge of the system clock CLK by comparing the reference time t.sub.CLref(OH) for insuring a low level time tCL of the system clock CLK and output hold time t.sub.OH, and which can sufficiently insure the data output setup time t.sub.OS and data output hold time t.sub.OH regardless of the frequency of the system clock by making the generation points of the internal clock to be varied depending on the frequency of the system clock.

    Abstract translation: 一种用于同步DRAM设备的数据输出缓冲器的内部时钟产生电路，其通过比较用于确保低电平的参考时间tCLref（OH）来产生参考系统时钟CLK的正边沿或下降沿的内部时钟 系统时钟CLK的时间tCL和输出保持时间tOH，并且可以通过使内部时钟的生成点变化来充分地确保数据输出建立时间tOS和数据输出保持时间tOH，而不管系统时钟的频率如何 取决于系统时钟的频率。

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