公开(公告)号：US09547318B1

公开(公告)日：2017-01-17

申请号：US14054488

申请日：2013-10-15

Applicant: Linear Technology Corporation

Inventor： David Dwelley ,  Jeffrey Heath ,  Kirk Su

IPC: G05F1/46 ,  G05F1/10

CPC classification number: G05F1/10 ,  B60R16/03 ,  G05F1/462 ,  H04L12/10 ,  H04L41/0681 ,  Y02D30/30 ,  Y02D30/32

Abstract: In a method performed by a Power Over Ethernet (PoE) system, Power Sourcing Equipment (PSE) provides data and voltage over Ethernet wires to a Powered Device (PD). The PD converts the PSE voltage to a regulated voltage by at least one DC-DC converter in the PD. A first load in the PD, such as a processor, operates in a standby mode during a standby period and draws a low current from the converter via a low current path. During this standby period, a high current load in the PD is disconnected and does not draw current. When the first load comes out of the standby mode and into an active mode, the converter supplies a relatively high current to the second load and the first load. In this way, the first load, if a processor, can be already booted up at the time the second load becomes active.

Abstract translation: 在通过以太网供电（PoE）系统执行的方法中，电源设备（PSE）通过以太网电缆将数据和电压提供给有源设备（PD）。 PD通过PD中的至少一个DC-DC转换器将PSE电压转换成调节电压。 PD中的第一负载（例如处理器）在待机期间在待机模式下工作，并且通过低电流路径从转换器抽取低电流。 在该待机期间，PD中的高电流负载断开，并且不抽出电流。 当第一个负载从待机模式进入活动模式时，转换器向第二个负载和第一个负载提供相对较高的电流。 以这种方式，如果处理器的第一个负载在第二个负载激活时可以被启动。

公开(公告)号：US20160353532A1

公开(公告)日：2016-12-01

申请号：US15147842

申请日：2016-05-05

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Joshua William Caldwell ,  Dongwon Kwon ,  Lucas Andrew Milner

IPC: H05B33/08

CPC classification number: H05B33/0815 ,  H02M3/04 ,  H02M3/156 ,  H02M3/3376 ,  H02M2001/0012 ,  H02M2001/0025 ,  H02M2001/0045 ,  H02M2001/0096 ,  H05B33/0812 ,  H05B33/0845 ,  H05B33/0857

Abstract: A method and system of driving an LED load. A driver is configured to deliver a level of current indicated by a control signal to the LED load when a PWM signal is ON and stop delivering the level of current when the PWM signal is OFF. An output capacitance element is coupled across a differential output of the LED driver. A feedback path, having a store circuit, is configured to store an information indicative of a first voltage level across the output capacitance element as a stored feedback reference signal just after the PWM signal is turned OFF. The feedback path causes the voltage across the output capacitance element to be at the first voltage level just before the PWM signal is turned ON.

Abstract translation: 驱动LED负载的方法和系统。 驱动器被配置为当PWM信号为ON时将控制信号指示的电流电平传递给LED负载，并且当PWM信号为OFF时停止传送电流电平。 输出电容元件跨越LED驱动器的差分输出耦合。 具有存储电路的反馈路径被配置为在PWM信号关闭之后存储指示输出电容元件上的第一电压电平的信息作为存储的反馈参考信号。 反馈路径使得输出电容元件两端的电压在PWM信号接通之前处于第一电压电平。

公开(公告)号：US09479142B1

公开(公告)日：2016-10-25

申请号：US14806478

申请日：2015-07-22

Applicant: Linear Technology Corporation

Inventor： John Perry Myers

IPC: H03K5/13 ,  H03H11/18 ,  H03K5/02 ,  H03K5/26 ,  H03H11/22 ,  H03K5/00

CPC classification number: H03H11/18 ,  H03B27/00 ,  H03D3/009 ,  H03D7/1441 ,  H03D7/1458 ,  H03D2200/0021 ,  H03D2200/0043 ,  H03H11/22 ,  H03K5/02 ,  H03K5/26 ,  H03K2005/00286

Abstract: A method and system of compensating for phase error. A phase error compensation circuit is configured to generate a phase-corrected quadrature Q output signal and a corresponding phase-corrected in-phase I output signal, the circuit includes a first transconductance circuit configured to convert a voltage signal related to an I input voltage signal to an I current signal. A second transconductance circuit is configured to convert a voltage signal related to a Q input signal to a Q current signal. A first multiplier circuit is configured to multiply the Q current signal times a Q scaling constant. A second multiplier circuit is configured to multiply the I current signal times an I scaling constant. An I summer sums the I current signal with the scaled Q signal. A Q summer sums the Q current signal with the scaled I signal.

Abstract translation: 一种补偿相位误差的方法和系统。 相位误差补偿电路被配置为产生相位校正的正交Q输出信号和对应的相位校正的同相I输出信号，该电路包括第一跨导电路，其被配置为将与I输入电压信号相关的电压信号 到I当前信号。 第二跨导电路被配置为将与Q输入信号相关的电压信号转换为Q电流信号。 第一乘法器电路被配置为将Q电流信号乘以Q缩放常数。 第二乘法器电路被配置为将I电流信号乘以I缩放常数。 I夏天用缩放的Q信号来计算I电流信号。 Q夏天与缩放的I信号相加Q电流信号。

公开(公告)号：US09454168B2

公开(公告)日：2016-09-27

申请号：US14706555

申请日：2015-05-07

Applicant: Linear Technology Corporation

Inventor： Amitkumar P. Patel ,  Carl Nelson

IPC: G05F1/575 ,  G05F1/563 ,  G05F1/59 ,  H02M1/00

CPC classification number: G05F1/575 ,  G05F1/563 ,  G05F1/59 ,  H02M2001/007

Abstract: In an LDO regulator, two feedback loops are created. The first feedback loop includes a high power PNP bipolar power transistor connected in series between the input voltage Vin terminal and the output voltage Vout terminal. The first feedback loop includes a first error amplifier that controls a drive transistor to drive the base of the power transistor such that Vout matches a set voltage Vset. This first feedback loop circuitry uses an operating voltage (the upper rail voltage) that is regulated by a second feedback loop and is approximately 300 mV greater than Vout. As a result, the control circuitry will be powered by a low ripple supply to improve output PSRR. Further, the power transistor is connected such that any noise in the input voltage is a common mode voltage across the base-emitter of the transistor.

Abstract translation: 在LDO调节器中，创建了两个反馈回路。 第一反馈回路包括串联连接在输入电压Vin端和输出电压Vout端之间的高功率PNP双极功率晶体管。 第一反馈回路包括第一误差放大器，其控制驱动晶体管驱动功率晶体管的基极，使得Vout匹配设定电压Vset。 该第一反馈回路电路使用由第二反馈回路调节的工作电压（上轨电压），并且比Vout大大约300mV。 因此，控制电路将由低纹波电源供电，以改善输出PSRR。 此外，功率晶体管被连接成使得输入电压中的任何噪声都是晶体管的基极 - 发射极两端的共模电压。

公开(公告)号：US09431319B2

公开(公告)日：2016-08-30

申请号：US14630239

申请日：2015-02-24

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Edward William Olsen ,  Leonard Shtargot ,  David Roy Ng ,  Jeffrey Kingan Witt

IPC: H01L23/10 ,  H01L23/367 ,  H01L23/31 ,  H01L23/48 ,  H01L23/433 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/3675 ,  H01L21/268 ,  H01L21/2855 ,  H01L21/2885 ,  H01L21/3105 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76879 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/3736 ,  H01L23/4334 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49861 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/16245 ,  H01L2224/19 ,  H01L2224/29111 ,  H01L2224/2912 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/14

Abstract: An integrated circuit package may include a semiconductor die, a heat spreader, and encapsulation material. The semiconductor die may contain an electronic circuit and exposed electrical connections to the electronic circuit. The heat spreader may be thermally-conductive and may have a first outer surface and a second outer surface substantially parallel to the first outer surface. The first outer surface may be affixed to all portions of a silicon side of the semiconductor die in a thermally-conductive manner. The encapsulation material may be non-electrically conductive and may completely encapsulate the semiconductor die and the heat spreader, except for the second surface of the heat spreader. The second surface of the heat spreader may be solderable and may form part of an exterior surface of the integrated circuit package.

Abstract translation: 集成电路封装可以包括半导体管芯，散热器和封装材料。 半导体管芯可以包含电子电路和暴露的电连接到电子电路。 散热器可以是导热的并且可以具有基本上平行于第一外表面的第一外表面和第二外表面。 第一外表面可以以导热方式固定到半导体管芯的硅侧的所有部分。 除了散热器的第二表面之外，封装材料可以是不导电的，并且可以完全封装半导体管芯和散热器。 散热器的第二表面可以是可焊接的并且可以形成集成电路封装的外表面的一部分。

公开(公告)号：US09391577B2

公开(公告)日：2016-07-12

申请号：US14670031

申请日：2015-03-26

Applicant: Linear Technology Corporation

Inventor： Petrus M. Stroet

IPC: H03F3/45 ,  H03G3/00 ,  H03G3/30 ,  H03F1/02 ,  H03F3/19 ,  H04L27/34 ,  H03F1/32 ,  H03G1/00

CPC classification number: H03G3/3042 ,  H03F1/0205 ,  H03F1/32 ,  H03F3/19 ,  H03F3/45098 ,  H03F2200/336 ,  H03F2200/451 ,  H03G1/0023 ,  H03G1/0029 ,  H04L27/34 ,  H04L27/368

Abstract: In a variable gain amplifier, a base of a bipolar first transistor receives a first differential input signal. The emitter of the first transistor is connected in series between a first resistor and a MOSFET coupled to ground. An output of the amplifier is a current through the collector. The conductivity of the MOSFET controls a gain of the amplifier. A bipolar second transistor receives a second differential input signal, and the second transistor provides a modulated gate voltage to the MOSFET. The drain voltage of the MOSFET is modulated by the first differential input signal and thus undesirably generates distortion. To reduce the distortion, the modulated gate voltage causes the AC component for a certain DC voltage at the drain of the MOSFET to be lowered, improving linearity. Since no current source is used, the amplifier has a large headroom, allowing operation using a low operating voltage.

Abstract translation: 在可变增益放大器中，双极性第一晶体管的基极接收第一差分输入信号。 第一晶体管的发射极串联在第一电阻和耦合到地的MOSFET之间。 放大器的输出是通过集电极的电流。 MOSFET的电导率控制放大器的增益。 双极性第二晶体管接收第二差分输入信号，并且第二晶体管向MOSFET施加调制的栅极电压。 MOSFET的漏极电压由第一差分输入信号调制，因此不期望地产生失真。 为了减小失真，调制栅极电压使MOSFET的漏极处的某一直流电压的交流分量降低，从而提高线性度。 由于没有使用电流源，所以放大器具有较大的余量，允许使用低工作电压进行工作。

公开(公告)号：US20160156341A1

公开(公告)日：2016-06-02

申请号：US15019394

申请日：2016-02-09

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Ciaran J. Brennan ,  Mukesh Kumar

IPC: H03K5/1532 ,  H01L27/088

CPC classification number: H03K5/1532 ,  H01L27/0883

Abstract: A maximum voltage selection circuit may include multiple inputs, each for receiving a different input voltage, an output for delivering the highest of the input voltages, and a voltage selection circuit. The voltage selection circuit may automatically select the input having the largest voltage magnitude, automatically deliver the voltage at the selected input to the output, and not draw quiescent operating current from any of the inputs. For each and every unique combination of two of the multiple inputs, the voltage selection circuit may include an enhancement mode FET with a channel connected in series between a first input of the unique combination of the two inputs and the output; a connection between the gate of the enhancement mode FET and the second input of the unique combination of the two inputs through the channel of a depletion mode FET; an additional enhancement mode FET with a channel connected in series between the second of the unique combination of the two inputs and the output; and a connection between the gate of the additional enhancement mode FET and the first of the unique combination of the two inputs through the channel of an additional depletion mode FET.

Abstract translation: 最大电压选择电路可以包括多个输入，每个用于接收不同的输入电压，用于输送最高输入电压的输出，以及电压选择电路。 电压选择电路可以自动选择具有最大电压幅值的输入端，将所选输入端的电压自动输出到输出端，并且不从任何输入端抽取静态工作电流。 对于多个输入中的两个的每个独特组合，电压选择电路可以包括增强型FET，其中通道串联连接在两个输入的唯一组合的第一输入和输出之间; 增强型FET的栅极与通过耗尽型FET的沟道的两个输入的独特组合的第二输入端之间的连接; 一个附加的增强型FET，其中通道串联在第二个两个输入和输出的唯一组合之间; 以及附加增强型FET的栅极和通过附加耗尽型FET的沟道的两个输入的唯一组合中的第一个之间的连接。

公开(公告)号：US20160156173A1

公开(公告)日：2016-06-02

申请号：US14956308

申请日：2015-12-01

Applicant: Linear Technology Corporation

Inventor： Andrew J. Gardner ,  Jeffrey L. Heath ,  David Dwelley

IPC: H02H3/20 ,  H02H3/087

CPC classification number: H02H3/202 ,  H02H3/06 ,  H02H3/207 ,  H02H11/002

Abstract: In one embodiment, a PoDL system includes a PSE that uses high side and low side circuit breakers that uncouple the PSE voltage source from the wire pair in the event that a fault is detected. Faults may include a temporary short to ground, or to a battery voltage, or between the wires. The breakers perform an automatic retry operation in the event the fault has been removed. The voltages on the wires in the wire pair may be monitored to determine whether the voltages are within a normal range or indicative of a fault condition. Other embodiments are disclosed.

Abstract translation: 在一个实施例中，PoDL系统包括使用高侧和低侧断路器的PSE，其在检测到故障的情况下将PSE电压源与电线对分离。 故障可能包括临时短路接地或电池电压，或电线之间。 断路器在故障消除的情况下执行自动重试操作。 可以监测线对中的导线上的电压，以确定电压是在正常范围内还是指示故障状态。 公开了其他实施例。

公开(公告)号：US09351352B2

公开(公告)日：2016-05-24

申请号：US14452335

申请日：2014-08-05

Applicant: Linear Technology Corporation

Inventor： Keith D. Szolusha

IPC: H05B33/08

CPC classification number: H05B33/08 ,  H05B33/0815 ,  H05B33/0818 ,  Y02B20/346

Abstract: A converter has a boost portion and a buck portion. The boost portion supplies a boosted voltage and includes a first inductor having a first end coupled to the input terminal, a first switch coupled to a second end of the first inductor to charge the first inductor when the first switch is in its on-state, and a first capacitor for being charged to the boosted voltage. The buck portion supplies an output voltage to a load that is less than the boosted voltage and includes a second inductor in series with the load, and a second switch in series with the second inductor and the load to charge the second inductor during an on-state of the second switch. A single controller IC receives feedback signals and controls the switches to have the same duty cycle to achieve a regulated load current or voltage with low EMI.

Abstract translation: A转换器具有升压部分和降压部分。 升压部分提供升压电压并且包括具有耦合到输入端子的第一端的第一电感器，耦合到第一电感器的第二端以在第一开关处于其导通状态时对第一电感器充电的第一开关， 以及用于被充电到升压电压的第一电容器。 降压部分将输出电压提供给小于升压电压的负载，并且包括与负载串联的第二电感器，以及与第二电感器和负载串联的第二开关，以在通电期间对第二电感器充电， 第二个开关的状态。 单个控制器IC接收反馈信号并控制开关具有相同的占空比，以实现具有低EMI的稳压负载电流或电压。

公开(公告)号：US20160142217A1

公开(公告)日：2016-05-19

申请号：US14945260

申请日：2015-11-18

Applicant: Linear Technology Corporation

Inventor： Andrew J. Gardner ,  Jeffrey L. Heath

IPC: H04L12/10

CPC classification number: H04L12/10 ,  B60L3/0069 ,  G01R31/024 ,  H02H3/16 ,  H04L12/40045 ,  H04L25/08 ,  H04L41/0681 ,  H04L43/0811 ,  Y04S40/166 ,  Y04S40/168

Abstract: Circuits and techniques are described for detecting a ground fault leak between the PSE and the PD. Prior to PoDL voltage being applied to the PD, a test switch is temporarily closed for sensing a voltage drop in a loop between the positive terminal of the PSE voltage source and any ground leakage path between the PSE and the PD. If the resistance of the ground leakage path is below a certain threshold, a fault is declared. A similar test may be performed without a test switch by supplying a known test current through the loop and sensing the voltage drop. Another test is to connect the positive terminal of the PSE voltage source to the loop and sense the resulting current. After the full PoDL voltage is applied to the PD, a ground fault may be detected by sensing the equivalence between the source and return PSE currents.

Abstract translation: 描述了用于检测PSE和PD之间的接地故障泄漏的电路和技术。 在PoDL电压施加到PD之前，测试开关暂时闭合，用于感测PSE电压源的正极端子与PSE和PD之间的任何接地泄漏路径之间的环路中的电压降。 如果地面泄漏路径的电阻低于一定阈值，则会声明故障。 可以通过提供已知的测试电流通过环路并感测电压降而不用测试开关进行类似的测试。 另一个测试是将PSE电压源的正极连接到环路并感测所得到的电流。 在将完整的PoDL电压施加到PD之后，可以通过感测源极和返回PSE电流之间的等效性来检测接地故障。