公开(公告)号：US07148099B2

公开(公告)日：2006-12-12

申请号：US10877836

申请日：2004-06-24

Applicant: Suman Datta ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Justin K. Brask ,  Robert S. Chau

Inventor： Suman Datta ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Justin K. Brask ,  Robert S. Chau

IPC: H01L21/8338

CPC classification number: H01L21/28247 ,  H01L21/26586 ,  H01L21/28238 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553

Abstract: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have a vertical portion that may be exposed to a silicon ion implantation. As a result of the implantation, the dielectric constant of a vertical portion may be reduced, reducing fringe capacitance.

Abstract translation: 在金属栅极更换工艺中，杯状栅极金属氧化物电介质可以具有可暴露于硅离子注入的垂直部分。 作为注入的结果，可以减小垂直部分的介电常数，减少边缘电容。

公开(公告)号：US07144783B2

公开(公告)日：2006-12-05

申请号：US10835791

申请日：2004-04-30

Applicant: Suman Datta ,  Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew Metz ,  Robert S. Chau

Inventor： Suman Datta ,  Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew Metz ,  Robert S. Chau

IPC: H01L21/336 ,  H01L21/4763

CPC classification number: H01L29/4983 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66606

Abstract: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have vertical portions that may be exposed to a reduction reaction. As a result of the reduction reaction, the vertical portions may be converted to metal, which adds to the existing gate electrode. In some cases, removing the vertical dielectric portions reduces fringe capacitance and may also advantageously slightly increased underdiffusion without adding heat, in some embodiments.

Abstract translation: 在金属栅极更换工艺中，杯状栅极金属氧化物电介质可以具有可能暴露于还原反应的垂直部分。 作为还原反应的结果，垂直部分可以转化为金属，这增加了现有的栅电极。 在一些实施例中，在一些实施例中，去除垂直电介质部分减少了边缘电容，并且还可以有利地稍微增加向下扩散而不加热。

公开(公告)号：US07129182B2

公开(公告)日：2006-10-31

申请号：US10704498

申请日：2003-11-06

Applicant: Justin K. Brask ,  Mark L. Doczy ,  Jack Kavalieros ,  Uday Shah ,  Matthew V. Metz ,  Robert S. Chau ,  Robert B. Turkot, Jr.

Inventor： Justin K. Brask ,  Mark L. Doczy ,  Jack Kavalieros ,  Uday Shah ,  Matthew V. Metz ,  Robert S. Chau ,  Robert B. Turkot, Jr.

IPC: H01L21/302

CPC classification number: C23F1/02 ,  H01L21/32134 ,  H01L21/823842

Abstract: A method for etching a metal layer is described. That method comprises forming a metal layer on a substrate, then exposing part of the metal layer to a wet etch chemistry that comprises an active ingredient with a diameter that exceeds the thickness of the metal layer.

Abstract translation: 描述了蚀刻金属层的方法。 该方法包括在基底上形成金属层，然后将金属层的一部分暴露于包含直径超过金属层厚度的活性成分的湿式蚀刻化学物质。

公开(公告)号：US07084038B2

公开(公告)日：2006-08-01

申请号：US11210220

申请日：2005-08-22

Applicant: Mark L. Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin K. Brask ,  Jack Kavalieros ,  Matthew V. Metz ,  Adrian B. Sherrill ,  Markus Kuhn ,  Robert S. Chau

Inventor： Mark L. Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin K. Brask ,  Jack Kavalieros ,  Matthew V. Metz ,  Adrian B. Sherrill ,  Markus Kuhn ,  Robert S. Chau

IPC: H01L21/336

CPC classification number: H01L21/0214 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/3144 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/517 ,  H01L29/518

Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成氧化物层，并在氧化物层上形成高k电介质层。 然后将氧化物层和高k电介质层在足够的温度下退火足够的时间以产生具有渐变介电常数的栅极电介质。

公开(公告)号：US06893927B1

公开(公告)日：2005-05-17

申请号：US10805880

申请日：2004-03-22

Applicant: Uday Shah ,  Mark L. Doczy ,  Justin K. Brask ,  Jack Kavalieros ,  Matthew V. Metz ,  Robert S. Chau

Inventor： Uday Shah ,  Mark L. Doczy ,  Justin K. Brask ,  Jack Kavalieros ,  Matthew V. Metz ,  Robert S. Chau

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/49

CPC classification number: H01L29/513 ,  H01L21/82345 ,  H01L21/823468 ,  H01L29/4966 ,  H01L29/517

Abstract: A method for making a semiconductor device is described. In that method, a metal layer is formed on a dielectric layer, which is formed on a substrate. After forming a masking layer on the metal layer, the sides of the masking layer are lined with a sacrificial layer.

Abstract translation: 描述制造半导体器件的方法。 在该方法中，在形成在基板上的电介质层上形成金属层。 在金属层上形成掩模层之后，掩模层的侧面衬有牺牲层。

公开(公告)号：US06855639B1

公开(公告)日：2005-02-15

申请号：US10632470

申请日：2003-08-01

Applicant: Justin K. Brask ,  Mark L. Doczy ,  Matthew V. Metz ,  John Barnak ,  Paul R. Markworth

Inventor： Justin K. Brask ,  Mark L. Doczy ,  Matthew V. Metz ,  John Barnak ,  Paul R. Markworth

IPC: H01L21/3063 ,  H01L21/28 ,  H01L21/311 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/28123 ,  H01L21/31111

Abstract: A high-K thin film patterning solution is disclosed to address structural and process limitations of conventional patterning techniques. Subsequent to formation of gate structures adjacent a high-K dielectric layer, a portion of the high-K dielectric layer material is reduced, preferably via exposure to hydrogen gas, to form a reduced portion of the high-K dielectric layer. The reduced portion may be selectively removed utilizing wet etch chemistries to leave behind a trench of desirable geometric properties.

Abstract translation: 公开了一种高K薄膜图形解决方案，以解决常规图案化技术的结构和工艺限制。 在与高K电介质层相邻形成栅极结构之后，优选通过暴露于氢气来降低高K电介质层材料的一部分，以形成高K电介质层的减少的部分。 可以使用湿蚀刻化学物质选择性地去除还原部分，以留下所需几何性质的沟槽。

公开(公告)号：US10804460B2

公开(公告)日：2020-10-13

申请号：US16097801

申请日：2016-07-01

Applicant: MD Tofizur Rahman ,  Christopher J. Wiegand ,  Brian Maertz ,  Daniel G. Ouellette ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  Daniel B. Bergstrom ,  Justin S. Brockman ,  Oleg Golonzka ,  Tahir Ghani ,  Intel Corporation

Inventor： MD Tofizur Rahman ,  Christopher J. Wiegand ,  Brian Maertz ,  Daniel G. Ouellette ,  Kevin P. O'Brien ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  Daniel B. Bergstrom ,  Justin S. Brockman ,  Oleg Golonzka ,  Tahir Ghani

IPC: H01L29/82 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  G11C11/16 ,  H01L43/02

Abstract: Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.

公开(公告)号：US20180350418A1

公开(公告)日：2018-12-06

申请号：US15779029

申请日：2015-12-24

Applicant: Brian S. Doyle ,  Elijah V. Karpov ,  Kaan Oguz ,  Kevin P. O'Brien ,  Charles C. Kuo ,  Mark L. Doczy ,  Uday Shah ,  Yih Wang

Inventor： Brian S. Doyle ,  Elijah V. Karpov ,  Kaan Oguz ,  Kevin P. O'Brien ,  Charles C. Kuo ,  Mark L. Doczy ,  Uday Shah ,  Yih Wang

IPC: G11C11/16 ,  G11C11/56 ,  H01L43/08 ,  H01L27/22

CPC classification number: G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C2211/5615 ,  H01L27/228 ,  H01L43/08

Abstract: Memory cells with improved tunneling magnetoresistance ratio (TMR) are disclosed. In some embodiments such devices may include a magnetoresistive tunnel junction (MTJ) element coupled in series with a tunneling magnetoresistance enhancement element (TMRE). The MTJ element and TMRE may each be configured to transition between high and low resistance states, e.g., in response to a voltage. In some embodiments, the MTJ and TMRE are configure such that when a read voltage is applied to the cell while the MTJ is in its low resistance state the TMRE is driven to is low resistance state, and when such voltage is applied while the MTJ is in its high resistance state, the TMRE remains in its high resistance state. Devices and systems including such memory cells are also disclosed.

公开(公告)号：US20150243336A1

公开(公告)日：2015-08-27

申请号：US14431607

申请日：2013-06-10

Applicant: Elijah V. KARPOV ,  Brian S. DOYLE ,  Kaan OGUZ ,  Satyarth SURI ,  Robert S. CHAU ,  Charles C. KUO ,  Mark L. DOCZY ,  David L. KENCKE ,  INTEL CORPORATION

Inventor： Elijah V. Karpov ,  Brian S. Doyle ,  Kaan Oguz ,  Satyarth Suri ,  Robert S. Chau ,  Charles S. Kuo ,  Mark L. Doczy ,  David L. Kencke

IPC: G11C11/16 ,  H01L43/08 ,  H01L43/02

CPC classification number: G11C11/1675 ,  B82Y25/00 ,  G11C11/15 ,  G11C11/16 ,  G11C11/161 ,  G11C11/5607 ,  H01F10/3254 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: Switching current in Spin-Transfer Torque Memory (STTM) can be decreased. A magnetic memory cell is driven with a first pulse on a write line of the memory cell to heat the cell. The cell is then driven with a second pulse on the write line to set the state of the cell.

Abstract translation: 旋转转矩存储器（STTM）中的切换电流可以减小。 磁存储单元用存储单元的写入线上的第一个脉冲驱动，以加热单元。 然后在写入线上用第二个脉冲驱动单元以设置单元的状态。

公开(公告)号：US08980650B2

公开(公告)日：2015-03-17

申请号：US14454682

申请日：2014-08-07

Applicant: Kaan Oguz ,  Mark L. Doczy ,  Brian Doyle ,  Uday Shah ,  David L. Kencke ,  Roksana Golizadeh Mojarad ,  Robert S. Chau

Inventor： Kaan Oguz ,  Mark L. Doczy ,  Brian Doyle ,  Uday Shah ,  David L. Kencke ,  Roksana Golizadeh Mojarad ,  Robert S. Chau

IPC: H01L21/00 ,  H01L43/12 ,  H01L43/08 ,  H01L29/82 ,  H01L27/22 ,  H01L43/10 ,  H01F10/32 ,  H01F10/193 ,  G11C11/16

CPC classification number: H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/18 ,  H01F10/1933 ,  H01F10/3254 ,  H01F10/3286 ,  H01F41/325 ,  H01L27/226 ,  H01L27/228 ,  H01L29/82 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.

Abstract translation: 适用于自旋转移转矩存储器（STTM）器件的磁隧道结（MTJ）包括垂直磁性层和通过结晶阻挡层与自由磁性层分离的一个或多个各向异性增强层。 在实施方案中，各向异性增强层改善了自由磁性层的垂直取向，而结晶势垒改善了隧道磁阻（TMR）比，同时自由磁层的晶体结构与隧穿层的结构更好地对准。