公开(公告)号：US20190237327A1

公开(公告)日：2019-08-01

申请号：US15886225

申请日：2018-02-01

Applicant: ASM IP Holding B.V.

Inventor： David Kohen ,  Nupur Bhargava ,  John Tolle ,  Vijay D'Costa

IPC: H01L21/02 ,  H01L29/165

Abstract: A method for depositing a semiconductor structure on a surface of a substrate is disclosed. The method may include: depositing a first group IVA semiconductor layer over a surface of the substrate; contacting an exposed surface of the first group IVA semiconductor layer with a first gas comprising a first chloride gas; and depositing a second group IVA semiconductor layer over a surface of the first group IVA semiconductor layer. Related semiconductor structures are also disclosed.

公开(公告)号：US20180323059A1

公开(公告)日：2018-11-08

申请号：US15957565

申请日：2018-04-19

Applicant: ASM IP Holding B.V.

Inventor： Nupur Bhargava ,  John Tolle ,  Joe Margetis ,  Matthew Goodman ,  Robert Vyne

IPC: H01L21/02 ,  H01L29/66 ,  C30B25/10 ,  C30B29/10

CPC classification number: H01L21/0262 ,  C30B25/02 ,  C30B25/10 ,  C30B29/06 ,  C30B29/10 ,  C30B29/52 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02573 ,  H01L21/02576 ,  H01L21/02579 ,  H01L29/66795

Abstract: A method for forming a silicon-containing epitaxial layer is disclosed. The method may include, heating a substrate to a temperature of less than approximately 950° C. and exposing the substrate to a first silicon source comprising a hydrogenated silicon source, a second silicon source, a dopant source, and a halogen source. The method may also include depositing a silicon-containing epitaxial layer wherein the dopant concentration within the silicon-containing epitaxial layer is greater than 3×1021 atoms per cubic centimeter.

公开(公告)号：US10053774B2

公开(公告)日：2018-08-21

申请号：US14738012

申请日：2015-06-12

Applicant: ASM IP HOLDING B.V.

Inventor： John Tolle ,  Eric Hill

IPC: C23C16/44 ,  C23C16/458 ,  H05B6/10 ,  C23C16/46 ,  C23C14/02 ,  C23C14/50 ,  C23C16/02

CPC classification number: C23C16/4405 ,  C23C14/021 ,  C23C14/50 ,  C23C16/0209 ,  C23C16/0218 ,  C23C16/458 ,  C23C16/4582 ,  C23C16/46 ,  H05B3/26 ,  H05B6/105

Abstract: A reactor system and related methods are provided which may include a heating element in a wafer tray. The heating element may be used to heat the wafer tray and a substrate or wafer seated on the wafer tray within a reaction chamber assembly, and may be used to cause sublimation of a native oxide of the wafer.

公开(公告)号：US09890456B2

公开(公告)日：2018-02-13

申请号：US14465252

申请日：2014-08-21

Applicant: ASM IP Holding B.V.

Inventor： John Tolle ,  Eric Hill ,  Jereld Lee Winkler

IPC: B01J19/24 ,  C23C16/46 ,  C23C16/50 ,  C23C16/52 ,  H01J37/32 ,  C23C16/452

CPC classification number: C23C16/46 ,  C23C16/452 ,  C23C16/50 ,  C23C16/52 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/3244 ,  H01J37/32816

Abstract: A system and method for providing intermediate reactive species to a reaction chamber are disclosed. The system includes an intermediate reactive species formation chamber fluidly coupled to the reaction chamber to provide intermediate reactive species to the reaction chamber. A pressure control device can be used to control an operating pressure of the intermediate reactive species formation chamber, and a heater can be used to heat the intermediate reactive species formation chamber to a desired temperature.

公开(公告)号：US20170278707A1

公开(公告)日：2017-09-28

申请号：US15450199

申请日：2017-03-06

Applicant: ASM IP Holding B.V.

Inventor： Joe Margetis ,  John Tolle ,  Gregory Bartlett ,  Nupur Bhargava

IPC: H01L21/02 ,  C23C16/455

CPC classification number: H01L21/02636 ,  C23C16/24 ,  C23C16/455 ,  C23C16/45514 ,  C23C16/45574 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262

Abstract: A gas distribution system is disclosed in order to obtain better film uniformity on a substrate in a cross-flow reactor. The better film uniformity may be achieved by an asymmetric bias on individual injection ports of the gas distribution system. The gas distribution may allow for varied tunability of the film properties.

公开(公告)号：US20170154770A1

公开(公告)日：2017-06-01

申请号：US14956115

申请日：2015-12-01

Applicant: ASM IP Holding B.V.

Inventor： Joe Margetis ,  John Tolle

IPC: H01L21/02 ,  H01L29/165 ,  H01L29/161

CPC classification number: H01L21/02535 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/161 ,  H01L29/165

Abstract: Methods of forming silicon germanium tin (SiGexGe1−xSny) films are disclosed. Exemplary methods include growing films including silicon, germanium and tin in an epitaxial chemical vapor deposition reactor. Exemplary methods are suitable for high volume manufacturing. Also disclosed are structures and devices including silicon germanium tin films.

公开(公告)号：US20170047446A1

公开(公告)日：2017-02-16

申请号：US14827177

申请日：2015-08-14

Applicant: ASM IP Holding B.V.

Inventor： Joe Margetis ,  John Tolle

IPC: H01L29/78 ,  C23C16/455 ,  H01L29/167 ,  H01L29/08 ,  H01L21/02 ,  H01L29/161

CPC classification number: C23C16/455 ,  C23C16/0272 ,  C23C16/30 ,  C23C16/45512 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/167

Abstract: Methods of forming p-type doped germanium-tin layers, systems for forming the p-type doped germanium-tin layers, and structures including the p-type doped germanium-tin layers are disclosed. The p-type doped germanium-tin layers include an n-type dopant, which allows relatively high levels of tin and/or p-type dopant to be included into the p-type doped germanium-tin layers.

Abstract translation: 公开了形成p型掺杂锗 - 锡层的方法，用于形成p型掺杂锗 - 锡层的系统，以及包括p型掺杂锗 - 锡层的结构。 p型掺杂的锗 - 锡层包括n型掺杂剂，其允许相对高水平的锡和/或p型掺杂剂包含在p型掺杂的锗 - 锡层中。

公开(公告)号：US09474163B2

公开(公告)日：2016-10-18

申请号：US14586438

申请日：2014-12-30

Applicant: ASM IP HOLDING B.V.

Inventor： John Tolle ,  Matthew G. Goodman

IPC: B05D3/02 ,  B05D3/04 ,  H05K3/00 ,  H01L21/02 ,  H01L21/306 ,  B05D3/00

CPC classification number: H01L21/0206 ,  B05D3/002 ,  B05D3/02 ,  B05D3/04 ,  B05D3/0433 ,  H01L21/02041 ,  H01L21/02046 ,  H01L21/306

Abstract: In some embodiments, a method for integrated circuit fabrication includes removing oxide material from a surface of a substrate, where the surface includes silicon and germanium. Removing the oxide material includes depositing a halogen-containing pre-clean material on a silicon oxide-containing surface and sublimating a portion of the halogen-containing pre-clean material to expose the silicon on the surface. A passivation film is deposited on the exposed silicon. The passivation film may include chlorine. The passivation film may prevent contamination of the silicon surface by chemical species from the later sublimation, which may be at a higher temperature than the earlier sublimation. Subsequently, a remaining portion of the halogen-containing pre-clean material and the passivation film are sublimated. A target material, such as a conductive material, may subsequently be deposited on the substrate surface.

Abstract translation: 在一些实施例中，用于集成电路制造的方法包括从衬底的表面去除氧化物材料，其中表面包括硅和锗。 除去氧化物材料包括将含卤素的预清洁材料沉积在含氧化硅的表面上并升华部分含卤素的预清洁材料以暴露表面上的硅。 钝化膜沉积在暴露的硅上。 钝化膜可以包括氯。 钝化膜可以防止来自稍后升华的化学物质对硅表面的污染，其可能处于比先前的升华更高的温度。 随后，将含卤素预清洁材料和钝化膜的剩余部分升华。 可以随后将诸如导电材料的靶材料沉积在衬底表面上。

公开(公告)号：US20150014816A1

公开(公告)日：2015-01-15

申请号：US14143719

申请日：2013-12-30

Applicant: ASM IP Holding B.V.

Inventor： Keith Doran Weeks ,  John Tolle ,  Matthew G. Goodman ,  Sandeep Mehta

IPC: H01L21/02 ,  H01L29/167 ,  H01L29/36 ,  H01L21/306

CPC classification number: H01L29/36 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32135

Abstract: A method of forming a semiconductor material incorporating an electrical dopant is disclosed. In one aspect, a method of incorporating dopant in a semiconductor film comprises forming a first semiconductor material incorporating the dopant at a first dopant concentration and preferentially etching a portion of the first semiconductor material, wherein etching leaves a first etched semiconductor material incorporating the dopant at a second dopant concentration higher than the first dopant concentration.

Abstract translation: 公开了一种形成掺有电掺杂剂的半导体材料的方法。 在一个方面，一种在半导体膜中掺入掺杂剂的方法包括以第一掺杂剂浓度形成掺入掺杂剂的第一半导体材料，并优先蚀刻第一半导体材料的一部分，其中蚀刻留下掺入掺杂剂的第一蚀刻半导体材料 第二掺杂剂浓度高于第一掺杂剂浓度。

公开(公告)号：US12195876B2

公开(公告)日：2025-01-14

申请号：US18372803

申请日：2023-09-26

Applicant: ASM IP Holding B.V.

Inventor： John Tolle ,  Joseph P. Margetis

IPC: C30B31/16 ,  C30B25/08 ,  C30B25/14 ,  C30B25/16 ,  C30B25/18 ,  H01L21/67

Abstract: Gas-phase reactor systems and methods suitable for use with precursors that are solid phase at room temperature and pressure are disclosed. The systems and methods as described herein can be used to, for example, form amorphous, polycrystalline, or epitaxial layers (e.g., one or more doped semiconductor layers) on a surface of a substrate.