公开(公告)号：US20170170291A1

公开(公告)日：2017-06-15

申请号：US14963397

申请日：2015-12-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert MULFINGER ,  Xusheng WU

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/4983 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7838 ,  H01L29/786 ,  H01L29/78654

Abstract: A method of controlling the facet height of raised source/drain epi structures using multiple spacers, and the resulting device are provided. Embodiments include providing a gate structure on a SOI layer; forming a first pair of spacers on the SOI layer adjacent to and on opposite sides of the gate structure; forming a second pair of spacers on an upper surface of the first pair of spacers adjacent to and on the opposite sides of the gate structure; and forming a pair of faceted raised source/drain structures on the SOI, each of the faceted source/drain structures faceted at the upper surface of the first pair of spacers, wherein the second pair of spacers is more selective to epitaxial growth than the first pair of spacers.

公开(公告)号：US20160328511A1

公开(公告)日：2016-11-10

申请号：US14704488

申请日：2015-05-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Yuping REN ,  Chin Teong LIM ,  Xusheng WU ,  Paul ACKMANN

IPC: G06F17/50 ,  H01L23/522

CPC classification number: H01L23/5226 ,  G03F1/36 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0207

Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.

Abstract translation: 公开了在IC设计的布局中所选择的区域（例如，包括关键区域）的识别和部分重新路由的方法以及所得到的设备。 实施例包括将IC器件的设计数据与制造IC器件的制造工艺标准进行比较; 在设计数据中，至少部分地基于所述布局区域中的金属段，互连段或其组合的接近来识别布局区域; 在所述布局区域中执行部分重路由以基本上满足所述准则，其中至少一个互连元件被移位或扩展; 并将部分重新路由集成到用于制造过程中的设计数据中。

公开(公告)号：US20160315084A1

公开(公告)日：2016-10-27

申请号：US14691960

申请日：2015-04-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng WU ,  HongLiang SHEN ,  Changyong XIAO ,  Jianhua YIN ,  Jie CHEN ,  Jin Ping LIU ,  Hong YU ,  Zhenyu HU ,  Lan YANG ,  Wanxun HE

IPC: H01L27/092 ,  H01L29/10 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L29/1033

Abstract: There is set forth herein in one embodiment a semiconductor structure having a first region and a second region. The first region can include fins of a first fin height and the second region can include fins of a second fin height.

Abstract translation: 这里在一个实施例中阐述了具有第一区域和第二区域的半导体结构。 第一区域可以包括第一翅片高度的翅片，并且第二区域可以包括具有第二翅片高度的翅片。

公开(公告)号：US20160225771A1

公开(公告)日：2016-08-04

申请号：US15096389

申请日：2016-04-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Jin Ping LIU

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/167 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/225

CPC classification number: H01L27/0924 ,  H01L21/2254 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823892 ,  H01L21/845 ,  H01L27/0922 ,  H01L29/0607 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/66803

Abstract: Methods are provided for fabricating fin structures. The methods include: fabricating at least one fin structure, the at least one fin structure having a doped middle portion separating an upper portion from a lower portion, and the fabricating comprising: providing an isolation layer in contact with the lower portion of the at least one fin structure; forming a doping layer above the isolation layer and in contact with the at least one fin structure; and annealing the doping layer to diffuse dopants therefrom into the at least one fin structure to form the doped middle portion thereof, wherein the isolation layer inhibits diffusion of dopants from the doping layer into the lower portion of the at least one fin structure.

Abstract translation: 提供了用于制造翅片结构的方法。 所述方法包括：制造至少一个翅片结构，所述至少一个翅片结构具有将上部与下部分隔开的掺杂中间部分，并且所述制造包括：提供与所述至少下部的下部接触的隔离层 一个鳍结构; 在所述隔离层上方形成掺杂层并与所述至少一个翅片结构接触; 以及退火所述掺杂层以将掺杂剂从其中扩散到所述至少一个鳍结构中以形成其掺杂的中间部分，其中所述隔离层抑制掺杂剂从所述掺杂层扩散到所述至少一个鳍结构的下部。

公开(公告)号：US20160225675A1

公开(公告)日：2016-08-04

申请号：US14611769

申请日：2015-02-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yan Ping SHEN ,  Min-hwa CHI ,  Xusheng WU ,  Weihua TONG ,  Haiting WANG

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L21/3215 ,  H01L21/285

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28568 ,  H01L21/3215 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method of forming RMG multi-WF layers for an nFET and pFET, and the resulting device are provided. Embodiments include forming a Si fin; forming a nFET RMG trench and a pFET RMG trench; forming a first Ti layer in the nFET and pFET RMG trenches; implanting N2 in the first Ti layer vertically at a 0° implant angle in the pFET RMG trench; annealing the N2 implanted first Ti layer to form a TiN layer in the pFET RMG trench; stripping un-reacted Ti of the first Ti layer; forming a second Ti layer in the nFET and pFET RMG trenches; implanting Al or C in the second Ti layer vertically at 0°; annealing the Al or C implanted second Ti layer to form TiAl or TiC at a bottom of the nFET and pFET RMG trenches, respectively; and filling the nFET and pFET RMG trenches with Al or W.

Abstract translation: 提供一种形成用于nFET和pFET的RMG多WF层的方法，以及所得到的器件。 实施例包括形成Si翅片; 形成nFET RMG沟槽和pFET RMG沟槽; 在nFET和pFET RMG沟槽中形成第一Ti层; 在pFET RMG沟槽中以0°注入角垂直注入第一Ti层中的N 2; 对N 2注入的第一Ti层退火以在pFET RMG沟槽中形成TiN层; 剥离第一Ti层的未反应的Ti; 在nFET和pFET RMG沟槽中形成第二Ti层; 在0°垂直方向将Al或C注入第二Ti层; 退火Al或C注入的第二Ti层，分别在nFET和pFET RMG沟槽的底部形成TiAl或TiC; 并用Al或W填充nFET和pFET RMG沟槽。

公开(公告)号：US20160155799A1

公开(公告)日：2016-06-02

申请号：US15002000

申请日：2016-01-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Changyong XIAO ,  Xiang HU ,  Wanxun HE

IPC: H01L29/06 ,  H01L29/20 ,  H01L29/161 ,  H01L27/092 ,  H01L29/16

CPC classification number: H01L29/0657 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/0259 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0692 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/201

Abstract: A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape.

Abstract translation: 非平面半导体结构包括混合的n型和p型凸起半导体结构，例如具有在其顶表面上生长的外延结构的散热片，例如外延硅和硅锗，天然生长成菱形。 外延结构的表面积通过去除其部分而增加，当另一种类型生长然后随后通过去除而修饰时，掩蔽每种类型。 移除可以与类似于Y形的相应凸起结构的颈部一起产生多头（例如，双头）外延结构。

公开(公告)号：US20160126336A1

公开(公告)日：2016-05-05

申请号：US14527250

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Changyong XIAO ,  Min-hwa CHI

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/311 ,  H01L29/417

CPC classification number: H01L29/66515 ,  H01L29/41775 ,  H01L29/42356 ,  H01L29/6653 ,  H01L29/66545

Abstract: Processes for forming merged CA/CB constructs and the resulting devices are disclosed. Embodiments include providing a replacement metal gate (RMG) between first and second sidewall spacers surrounded by an insulator on a substrate, the RMG having a dielectric layer directly on the first and second sidewall spacers and having metal on the dielectric layer; providing an oxide layer over the insulator, the first and second sidewall spacers, and the RMG; forming a source/drain contact hole through the oxide layer and the insulator, adjacent to the first sidewall spacer; forming a gate contact hole through the oxide layer over the source/drain contact hole and extending to the metal of the RMG; enlarging the source/drain contact hole to the metal of the RMG; and filling the enlarged source/drain contact hole and gate contact hole with metal.

Abstract translation: 公开了形成合并的CA / CB结构和所得到的设备的过程。 实施例包括在由衬底上的绝缘体围绕的第一和第二侧壁间隔之间提供置换金属栅极（RMG），RMG直接在第一和第二侧壁间隔物上并且在电介质层上具有金属; 在绝缘体上方提供氧化物层，第一和第二侧壁间隔物以及RMG; 形成与所述第一侧壁间隔物相邻的所述氧化物层和所述绝缘体的源极/漏极接触孔; 在源极/漏极接触孔上形成通过氧化物层的栅极接触孔并延伸到RMG的金属; 将源极/漏极接触孔扩大到RMG的金属; 并用金属填充放大的源极/漏极接触孔和栅极接触孔。

公开(公告)号：US20150332963A1

公开(公告)日：2015-11-19

申请号：US14281454

申请日：2014-05-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Changyong XIAO ,  Min-hwa CHI

IPC: H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/28518 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/485 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor, planar or non-planar (e.g., FinFET), includes T-shaped contacts to the source, drain and gate. The top portion of the T-shaped contact is wider than the bottom portion, the bottom portion complying with design rule limits. A conductor-material filled trench through a multi-layer etching stack above the transistor provides the top portions of the T-shaped contacts. Tapered spacers along inner sidewalls of the top contact portion prior to filling allow for etching a narrower bottom trench down to the gate, and to the source/drain for silicidation prior to filling.

Abstract translation: 晶体管，平面或非平面（例如，FinFET）包括到源极，漏极和栅极的T形接触。 T形接触件的顶部比底部宽，底部符合设计规则限制。 通过晶体管上方的多层蚀刻堆叠的导体材料填充沟槽提供了T形触头的顶部。 在填充之前，顶部接触部分的内侧壁上的锥形间隔物允许在填充之前将较窄的底部沟槽蚀刻到栅极和源极/漏极以进行硅化。

公开(公告)号：US20150318217A1

公开(公告)日：2015-11-05

申请号：US14267611

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng WU ,  Xiang HU ,  Changyong XIAO ,  Wanxun HE

IPC: H01L21/8238 ,  H01L21/02 ,  H01L29/201 ,  H01L29/161 ,  H01L29/16 ,  H01L21/306 ,  H01L27/092

CPC classification number: H01L29/0657 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/0259 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0692 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/201

Abstract: A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape.

Abstract translation: 非平面半导体结构包括混合的n型和p型凸起半导体结构，例如具有在其顶表面上生长的外延结构的散热片，例如外延硅和硅锗，天然生长成菱形。 外延结构的表面积通过去除其部分而增加，当另一种类型生长然后随后通过去除而修饰时，掩蔽每种类型。 移除可以与类似于Y形的相应凸起结构的颈部一起产生多头（例如，双头）外延结构。