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    Timing control for unmatched signal receiver
    33.
    发明授权
    Timing control for unmatched signal receiver 有权

    公开(公告)号：US09658642B2

    公开(公告)日：2017-05-23

    申请号：US14038537

    申请日：2013-09-26

    Applicant: Intel Corporation

    Inventor： Christopher P. Mozak

    IPC: G06F1/00 ,  H04L7/00 ,  G06F1/04 ,  G11C7/22 ,  H03L7/00 ,  G11C27/02

    CPC classification number: G06F1/04 ,  G06F13/4291 ,  G11C7/222 ,  G11C27/02 ,  H03L7/00 ,  H04L7/0008

    Abstract: A device with an I/O interface includes a replica clock distribution path matched to a clock distribution path of an unmatched receiver circuit. The device can monitor changes in delay in the replica path, and adjust delay in the real clock distribution path in response to the delay changes detected in the replica path. The receiver circuit includes a data path and a clock distribution network in an unmatched configuration. A ring oscillator circuit includes a replica clock distribution network matched to the real clock distribution network. Thus, delay changes detected for the replica clock distribution network indicates a change in delay in the real clock distribution network, which can be compensated accordingly.

    Variable weak leaker values during read operations
    34.
    发明授权
    Variable weak leaker values during read operations 有权
    读取操作期间可变的弱弱值

    公开(公告)号：US09583176B1

    公开(公告)日：2017-02-28

    申请号：US14864435

    申请日：2015-09-24

    Applicant: Intel Corporation

    Inventor： Christopher P. Mozak

    IPC: G11C7/00 ,  G11C11/4096 ,  G11C11/4076 ,  G11C7/22

    CPC classification number: G11C11/4096 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076

    Abstract: Systems, apparatuses and methods may provide for determining a status of an enable signal and selecting a leaker resistance from a plurality of leaker resistances based at least in part on the status of the enable signal. Additionally, the selected leaker resistance may be applied to a data strobe line of a memory bus. In one example, the selected leaker resistance reduces ringback noise on the data strobe line.

    Abstract translation: 系统，装置和方法可以至少部分地基于使能信号的状态来提供确定使能信号的状态并从多个漏电阻中选择一个漏电阻。 另外，所选择的漏电阻可以应用于存储器总线的数据选通线。 在一个示例中，所选择的漏电阻降低了数据选通线上的环背噪声。

    Power gating for termination power supplies
    35.
    发明授权
    Power gating for termination power supplies 有权
    电源门控端接电源

    公开(公告)号：US09507408B2

    公开(公告)日：2016-11-29

    申请号：US13629008

    申请日：2012-09-27

    Applicant: Intel Corporation

    Inventor： Xiuting C. Man ,  Christopher P. Mozak ,  Shaun M. Conrad ,  Jeffery L. Krieger ,  Philip R. Lehwalder ,  Inder M. Sodhi

    IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32

    CPC classification number: G06F1/3296 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

    Abstract: Power gating control architectures. A memory device having at least a memory array and input/output (I/O) lines terminated on the memory device with termination circuitry coupled to receive a termination supply voltage (Vtt) with power gating circuitry to selectively gate the termination supply voltage in response to a power gating control signal (VttControl) is coupled with a processing core coupled with the memory device, the processing core to selectively assert and deassert the VttControl signal.

    Abstract translation: 电力门控控制架构。 存储器件具有至少存储器阵列和终端于存储器件上的输入/输出（I / O）线，其中终端电路被耦合以用电源门控电路接收终端电源电压（Vtt），以响应于选择性地对终端电源电压进行选通 电力门控控制信号（VttControl）与与存储器件耦合的处理核心耦合，处理核心选择性地断言和解除VttControl信号。

    Periodic training for unmatched signal receiver
    37.
    发明授权
    Periodic training for unmatched signal receiver 有权
    定期训练不匹配的信号接收机

    公开(公告)号：US09218575B2

    公开(公告)日：2015-12-22

    申请号：US14018217

    申请日：2013-09-04

    Applicant: Intel Corporation

    Inventor： Christopher P. Mozak ,  James A. McCall

    IPC: G06F3/00 ,  G06F13/00 ,  G06N99/00 ,  G05B13/02

    CPC classification number: G06N99/005 ,  G05B13/02 ,  G11C7/1093 ,  G11C29/022 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2207/2254

    Abstract: I/O parameters are adjusted based on a number of errors detected in a received training signal. A controller device sends the training signal while a memory device is in a training mode. The memory device samples the training signal and the system causes an adjustment to at least one I/O parameter based on a detected number of errors. Either the controller or the memory device can perform the error detection, depending on the configuration of the system. Either an I/O parameter of the controller or an I/O parameter of the memory device can be adjusted, depending on the configuration of the system.

    Abstract translation: 基于在接收到的训练信号中检测到的错误的数量来调整I / O参数。 控制器设备在存储设备处于训练模式时发送训练信号。 存储器件采样训练信号，并且系统基于检测到的错误数量对至少一个I / O参数进行调整。 控制器或存储设备可以根据系统的配置执行错误检测。 根据系统的配置，可以调整控制器的I / O参数或存储设备的I / O参数。

    Transaction-level testing of memory I/O and memory device
    38.
    发明授权
    Transaction-level testing of memory I/O and memory device 有权
    内存I / O和内存设备的事务级别测试

    公开(公告)号：US08996934B2

    公开(公告)日：2015-03-31

    申请号：US13631961

    申请日：2012-09-29

    Applicant: Intel Corporation

    Inventor： Christopher P. Mozak ,  Theodore Z. Schoenborn ,  James M. Shehadi

    IPC: G11C29/00 ,  G11C29/08 ,  G11C29/56

    CPC classification number: G11C29/08 ,  G11C29/56 ,  G11C2029/5602

    Abstract: A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine receives a command to cause it to generate transactions to implement a memory test. The command identifies the test to implement, and the test engine generates one or more memory access transactions to implement the test on the memory device. The test engine passes the transactions to the memory controller, which can schedule the commands with its scheduler. Thus, the transactions cause deterministic behavior in the memory device because the transactions are executed as provided, while at the same time testing the actual operation of the device.

    Abstract translation: 存储器子系统包括耦合到存储器控制器的测试引擎，其可以绕过存储器地址解码器来向存储器控制器提供存储器访问事务。 测试引擎接收到一个命令，使其生成事务以实现内存测试。 该命令标识要实现的测试，并且测试引擎生成一个或多个存储器访问事务以在存储器设备上实现测试。 测试引擎将事务传递到内存控制器，可以使用其调度程序来调度命令。 因此，交易在存储设备中引起确定性行为，因为交易按照提供的方式执行，同时测试设备的实际操作。

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