公开(公告)号：US20240222238A1

公开(公告)日：2024-07-04

申请号：US18091543

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Srinivas Venkata Ramanuja Pietambaram ,  Bai Nie ,  Gang Duan ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/15

CPC classification number: H01L23/49811 ,  H01L23/15 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/81815

Abstract: An integrated circuit device substrate includes a glass substrate with a first major surface comprising a plateau region, a cavity region, and a wall between the plateau region and the cavity region. The first major surface includes thereon a first dielectric region, and the plateau region includes a plurality of conductive pillars. A second major surface of the glass substrate opposite the first major surface includes thereon a second dielectric layer, wherein the second dielectric layer includes at least one dielectric-free window underlying the cavity region.

公开(公告)号：US20240215269A1

公开(公告)日：2024-06-27

申请号：US18086232

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington

IPC: H10B80/00 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13023

Abstract: An electronic system includes a substrate that includes a glass core layer including a cavity formed through the glass core layer; at least one active component die disposed in the cavity; a first buildup layer contacting a first surface of the glass core layer and a first surface of the at least one active component die, wherein the first buildup layer includes electrically conductive interconnect contacting the at least one active component die and extending to a first surface of the substrate; a second buildup layer contacting a second surface of the glass core layer and a second surface of the at least one active component die; and one or more solder bumps on a second surface of the substrate and contacting the second surface of the at least one active component die.

公开(公告)号：US20240213116A1

公开(公告)日：2024-06-27

申请号：US18069507

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Kyle Arrington ,  Bohan Shan ,  Haobo Chen ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Dingying Xu ,  Xiaoying Guo ,  Bai Nie ,  Srinivas Pietambaram ,  Gang Duan

IPC: H01L23/473 ,  H01L23/15 ,  H01L23/467 ,  H01L23/538

CPC classification number: H01L23/473 ,  H01L23/15 ,  H01L23/467 ,  H01L23/5383

Abstract: Methods, systems, apparatus, and articles of manufacture to cool integrated circuit packages having glass substrates are disclosed. An example glass core of an integrated circuit (IC) package disclosed herein includes a fluid inlet to receive a cooling fluid, a fluid outlet, and a channel to fluidly couple the fluid inlet to the fluid outlet, the cooling fluid to flow through the channel from the fluid inlet to the fluid outlet, the channel fluidly isolated from one or more vias extending between a first surface and a second surface of the glass core.

公开(公告)号：US11574851B2

公开(公告)日：2023-02-07

申请号：US16287116

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Omkar Karhade ,  Ram Viswanath ,  Je-Young Chang ,  Weihua Tang ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Kumar Singh

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/427 ,  H01L25/18 ,  H01L21/56

Abstract: An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.

公开(公告)号：US11545407B2

公开(公告)日：2023-01-03

申请号：US16244748

申请日：2019-01-10

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Manish Dubey ,  Ravindranath Mahajan ,  Ram Viswanath ,  James C. Matayabas, Jr.

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H01L21/48

Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.

公开(公告)号：US09611372B2

公开(公告)日：2017-04-04

申请号：US15047866

申请日：2016-02-19

Applicant: Intel Corporation

Inventor： Yonghao Xiu ,  Nisha Ananthakrishnan ,  Yiqun Bai ,  Arjun Krishnan

IPC: H01L21/50 ,  C08K3/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29

CPC classification number: C08K3/013 ,  H01L21/563 ,  H01L23/295 ,  H01L24/17 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L2224/131 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/29499 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2924/01006 ,  H01L2924/04642 ,  H01L2924/0493 ,  H01L2924/053 ,  H01L2924/0533 ,  H01L2924/05341 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/186 ,  H01L2924/0665 ,  H01L2924/05032 ,  H01L2924/014

Abstract: An underfill composition comprises a curable resin, a plurality of filler particles loaded within the resin, the filler particles comprising at least 50 weight % of the underfill composition. The filler particles comprise first filler particles having a particle size of from 0.1 micrometers to 15 micrometers and second filler particles having a particle size of less than 100 nanometers. A viscosity of the underfill composition is less than a viscosity of a corresponding composition not including the second filler particles.

公开(公告)号：US20160343591A1

公开(公告)日：2016-11-24

申请号：US15225678

申请日：2016-08-01

Applicant: INTEL CORPORATION

Inventor： Suriyakala Ramalingam ,  Manish Dubey ,  Hsin-Yu Li ,  Michelle S. Phen-Givoni ,  Hitesh Arora ,  Nisha Ananthakrishnan ,  Yiqun Bai ,  Yonghao Xiu ,  Rajendra C. Dias

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/29

Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于具有以通常随机分布图案排列的填充颗粒的底部填充层的集成电路（IC）封装的技术和配置。 在一些实施例中，通过对IC封装组件的一个或多个部件上的静电电荷，通过对填料进行表面处理以减少填充剂电荷，可以通过施加电力来抵抗填料颗粒的大致随机分布图案 通过使用相对较低的最大填充剂粒度的底部填充材料和/或通过在相对低的温度下快速固化底部填充层，使底部填充材料的填料颗粒在与重力方向相反的方向上。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160240395A1

公开(公告)日：2016-08-18

申请号：US15139265

申请日：2016-04-26

Applicant: Intel Corporation

Inventor： Yiqun Bai ,  Yuying Wei ,  Arjun Krishnan ,  Suriyakala Ramalingam ,  Yonghao Xiu ,  Beverly J. Canham ,  Sivakumar Nagarajan ,  Saikumar Jayaraman ,  Nisha Ananthakrishnan

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/29

CPC classification number: H01L21/563 ,  H01L23/293 ,  H01L23/295 ,  H01L23/296 ,  H01L24/13 ,  H01L2224/16225 ,  H01L2224/29647 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法和结构可以包括用硫醇粘合促进剂，唑偶合剂，表面改性填料和基于过氧化物的交联聚合物化学物质之一改性底部填充材料，以便利用本文的实施方案极大地增强包装结构中的粘合性。

公开(公告)号：US20250110295A1

公开(公告)日：2025-04-03

申请号：US18478077

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Saikumar Jayaraman ,  Yiqun Bai ,  Fan Fan ,  Dingying Xu

IPC: G02B6/42 ,  C09J171/02

Abstract: A set of optical fibers are set within grooves a substrate to align the optical fibers with a waveguide associated with photonic processing circuitry. The set of optical fibers are adhered within the grooves using a polyethylene oxide (PEO)-based adhesive. The PEO-based adhesive may have a refractive index matched to the refractive index of one or both of the optical fibers or the waveguide.

公开(公告)号：US12099245B2

公开(公告)日：2024-09-24

申请号：US17125481

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Asako Toda ,  Chia-Pin Chiu ,  Xiaoqian Li ,  Yiqun Bai

IPC: G02B6/42

CPC classification number: G02B6/4253 ,  G02B6/4243 ,  G02B6/4268 ,  G02B6/4269

Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, where the package substrate comprises a recessed edge. In an embodiment, a compute die is on the package substrate, and an optics die on the package substrate and overhanging the recessed edge of the package substrate. In an embodiment, an integrated heat spreader (IHS) is over the compute die and the optics die. In an embodiment, a lid covers the recess in the package substrate.