公开(公告)号：US20240105608A1

公开(公告)日：2024-03-28

申请号：US17935582

申请日：2022-09-27

Applicant: International Business Machines Corporation

Inventor： Nicholas Anthony Lanzillo ,  Albert M. Chu ,  Brent A. Anderson ,  Lawrence A. Clevenger ,  Ruilong Xie ,  Reinaldo Vega

IPC: H01L23/528 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/5226

Abstract: A method for forming a semiconductor device includes forming a front side of the semiconductor device, the front side comprising a metal wire M2, and a plurality of power rails coupled to the M2. Further, the method includes forming a through silicon via (TSV) from a back side of the semiconductor device to the front side, the TSV connecting a first power rail of the front side with a metal wire M1 on the back side. Further, the method includes forming a power delivery network on the back side, the TSV providing power from the power delivery network to the front side.

公开(公告)号：US20240079462A1

公开(公告)日：2024-03-07

申请号：US17901133

申请日：2022-09-01

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Brent A. Anderson ,  Lawrence A. Clevenger ,  Nicholas Anthony Lanzillo ,  Reinaldo Vega ,  Albert M. Chu

IPC: H01L29/417 ,  H01L21/78 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41741 ,  H01L21/7806 ,  H01L27/088 ,  H01L29/401 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor structure comprises a vertical transistor, a first contact connecting to a source/drain region at a first side of the vertical transistor, a second contact extending from the first side of the vertical transistor to a second side of the vertical transistor, and an interconnect structure at the first side of the vertical transistor connecting the first contact to the second contact.

公开(公告)号：US20240071920A1

公开(公告)日：2024-02-29

申请号：US17896278

申请日：2022-08-26

Applicant: International Business Machines Corporation

Inventor： Nicholas Anthony Lanzillo ,  Brent A. Anderson ,  Albert M. Chu ,  Lawrence A. Clevenger ,  Ruilong Xie ,  Reinaldo Vega

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76883 ,  H01L23/53223

Abstract: A semiconductor apparatus includes a substrate; a first conductive feature disposed on the substrate, the first conductive feature comprising a conductive material; a second conductive feature disposed on the substrate, the second conductive feature comprising the conductive material; a dielectric material at least partially surrounding the first conductive feature and the second conductive feature; and an interconnect between the first conductive feature and the second conductive feature, the interconnect comprising the conductive material integral with the first conductive feature and the second conductive feature and extending through the dielectric material and below the first conductive feature and the second conductive feature.

公开(公告)号：US11894423B2

公开(公告)日：2024-02-06

申请号：US17677007

申请日：2022-02-22

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Dechao Guo ,  Ruqiang Bao ,  Junli Wang ,  Lan Yu ,  Reinaldo Vega ,  Adra Carr

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/08

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7851

Abstract: Techniques are provided to fabricate semiconductor devices having a nanosheet field-effect transistor device disposed on a semiconductor substrate. The nanosheet field-effect transistor device includes a nanosheet stack structure including a semiconductor channel layer and a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure. A trench formed in the source/drain region is filled with a metal-based material. The metal-based material filling the trench in the source/drain region mitigates the effect of source/drain material overfill on the contact resistance of the semiconductor device.

公开(公告)号：US11710699B2

公开(公告)日：2023-07-25

申请号：US17463704

申请日：2021-09-01

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Jingyun Zhang ,  Reinaldo Vega ,  Kangguo Cheng

IPC: H01L23/52 ,  H01L23/528 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/265

CPC classification number: H01L23/5286 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7827

Abstract: A CFET includes a fin that has a bottom channel portion, a top channel portion, and a channel isolator between the bottom channel portion and the top channel portion. The CFET further includes a source and drain stack that has a bottom source or drain (S/D) region connected to the bottom channel portion, a top S/D region connected to the top channel portion, a source-drain isolator between the bottom S/D region and the top S/D region. The CFET further includes a spacer foot physically connected to a base sidewall portion of the bottom S/D region and a buried S/D contact that is physically connected to an upper sidewall portion of the bottom S/D region. The CFET may further include a common gate around the bottom channel portion, around the top channel portion, and around the channel isolator.

公开(公告)号：US20230176115A1

公开(公告)日：2023-06-08

申请号：US17540835

申请日：2021-12-02

Applicant: International Business Machines Corporation

Inventor： Kushagra Sinha ,  Pablo Nieves ,  Reinaldo Vega

IPC: G01R31/28

CPC classification number: G01R31/2891 ,  G01R31/2889

Abstract: A testing apparatus comprises a first electromagnet. The first electromagnet can be configured to expose a first test device to a first electromagnetic field. The testing apparatus also comprises a second electromagnet. The second electromagnet can be configured to expose a second test device to a second electromagnetic field.

公开(公告)号：US20230094719A1

公开(公告)日：2023-03-30

申请号：US17490454

申请日：2021-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng Chi ,  Takashi Ando ,  Reinaldo Vega ,  Praneet Adusumilli

IPC: G03F1/36 ,  G03F1/92 ,  G03F1/38

Abstract: A memory device is provided. The memory device includes a main feature disposed beneath a surface of a photolithographic mask. The memory device further includes at least one Sub-Resolution Assistant Feature (SRAF) proximate to the main feature beneath the surface. The main feature has an electrical conductivity based on an area relationship with the at least one SRAF.

公开(公告)号：US20230077912A1

公开(公告)日：2023-03-16

申请号：US17475970

申请日：2021-09-15

Applicant: International Business Machines Corporation

Inventor： Praneet Adusumilli ,  Kevin W. Brew ,  Takashi Ando ,  Reinaldo Vega

IPC: H01L45/00

Abstract: A memory, system, and method to improve integration density while maintaining thermal efficiency through a phase change memory cell with a superlattice based thermal barrier. The phase change memory may include a bottom electrode. The phase change memory may also include an active phase change material. The phase change memory may also include a superlattice thermal barrier proximately connected to the active phase change material. The phase change memory may also include a top electrode proximately connected to the superlattice thermal barrier. The system may include the phase change memory cell. The method for forming a phase change memory may include depositing an active phase change material on a bottom electrode. The method may also include depositing a superlattice thermal barrier proximately connected to the active phase change material. The method may also include depositing a top electrode proximately connected to the superlattice thermal barrier.

公开(公告)号：US11430954B2

公开(公告)日：2022-08-30

申请号：US17106286

申请日：2020-11-30

Applicant: International Business Machines Corporation

Inventor： Praneet Adusumilli ,  Anirban Chandra ,  Takashi Ando ,  Cheng Chi ,  Reinaldo Vega

IPC: H01L45/00

Abstract: A mushroom-type Phase-Change Memory (PCM) device includes a substrate, a lower interconnect disposed in the substrate, a first dielectric layer disposed on the substrate, a bottom electrode disposed in the first dielectric layer and extending above an upper surface of the first dielectric layer, a type drift-mitigation liner encircling an upper portion of the bottom electrode extending above the upper surface of the first dielectric layer, a PCM element disposed on the liner and an upper surface of the bottom electrode, a top electrode disposed on the PCM element, and a second dielectric layer disposed on an exposed portion of the first dielectric layer and the top electrode, wherein the second dielectric layer is disposed on sidewalls of the liner, the PCM element, and the top electrode.

公开(公告)号：US11244864B2

公开(公告)日：2022-02-08

申请号：US16854276

申请日：2020-04-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Reinaldo Vega ,  Alexander Reznicek ,  Kangguo Cheng

IPC: H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L27/088 ,  H01L21/311 ,  H01L29/06 ,  H01L29/10

Abstract: A method for fabricating a semiconductor device includes forming a shared source/drain connection at a first planar level to connect a first source/drain contact structure disposed on a first source/drain region to a second source/drain contact structure disposed on a second source/drain region, and forming a shared gate connection to connect a first gate structure to a second gate structure. The shared gate connection is formed at a second planar level different from the first planar level to reduce parasitic capacitance between the shared source/drain connection and the shared gate connection.