公开(公告)号：US09373585B2

公开(公告)日：2016-06-21

申请号：US14489358

申请日：2014-09-17

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar ,  Charles G. Woychik ,  Guilian Gao ,  Arkalgud R. Sitaram

IPC: H01L23/52 ,  H01L23/48 ,  H01L23/532 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/5328 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/49811 ,  H01L23/5226 ,  H01L24/83 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/4823 ,  H01L2224/73203 ,  H01L2224/73257 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2924/014

Abstract: An interconnect (124) suitable for attachment of integrated circuit assemblies to each other comprises a polymer member (130), possibly dielectric, coated with a conductive material (144) which provides one or more conductive lines. In some embodiments, the conductive material covers a part, but not all, of the polymer member. In some embodiments, multiple conductive lines are formed on the polymer member. In some embodiments, the polymer member is conductive. Such interconnects replace metal bond wires in some embodiments. Other features are also provided.

Abstract translation: 适于将集成电路组件彼此连接的互连（124）包括涂覆有提供一个或多个导电线的导电材料（144）的聚合物构件（130），可能是电介质。 在一些实施例中，导电材料覆盖聚合物构件的一部分但并非全部。 在一些实施例中，在聚合物构件上形成多个导电线。 在一些实施方案中，聚合物构件是导电的。 在一些实施例中，这种互连替代金属接合线。 还提供其他功能。

公开(公告)号：US20210035954A1

公开(公告)日：2021-02-04

申请号：US17074401

申请日：2020-10-19

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Arkalgud R. Sitaram

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/311 ,  H01L21/02 ,  H01L23/64

Abstract: Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct-bonded together at the same bonding interface.

公开(公告)号：US20190098271A1

公开(公告)日：2019-03-28

申请号：US16206549

申请日：2018-11-30

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Guilian Gao ,  Arkalgud R. Sitaram

IPC: H04N9/43 ,  H01L27/146 ,  H04N9/76 ,  H04N5/33 ,  H04N9/04 ,  H04N9/097 ,  G02B27/10 ,  G06T1/20 ,  H01L31/0232 ,  H01L31/028 ,  H01L31/0296 ,  H01L31/0304 ,  H01L31/032 ,  H04N5/374

Abstract: HD color video using monochromatic CMOS image sensors integrated in a 3D package is provided. An example 3DIC package for color video includes a beam splitter to partition received light of an image stream into multiple light outputs. Multiple monochromatic CMOS image sensors are each coupled to one of the multiple light outputs to sense a monochromatic image stream at a respective component wavelength of the received light. Each monochromatic CMOS image sensor is specially constructed, doped, controlled, and tuned to its respective wavelength of light. A parallel processing integrator or interposer chip heterogeneously combines the respective monochromatic image streams into a full-spectrum color video stream, including parallel processing of an infrared or ultraviolet stream. The parallel processing of the monochromatic image streams provides reconstruction to HD or 4K HD color video at low light levels. Parallel processing to one interposer chip also enhances speed, spatial resolution, sensitivity, low light performance, and color reconstruction.

公开(公告)号：US20180366446A1

公开(公告)日：2018-12-20

申请号：US16020654

申请日：2018-06-27

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Arkalgud R. Sitaram

IPC: H01L25/065 ,  H01L21/02 ,  H01L23/00 ,  H01L25/00 ,  H01L23/64 ,  H01L21/311

Abstract: Capacitive coupling of integrated circuit die components and other conductive areas is provided. Each component to be coupled has a surface that includes at least one conductive area, such as a metal pad or plate. An ultrathin layer of dielectric is formed on at least one surface to be coupled. When the two components, e.g., one from each die, are permanently contacted together, the ultrathin layer of dielectric remains between the two surfaces, forming a capacitor or capacitive interface between the conductive areas of each respective component. The ultrathin layer of dielectric may be composed of multiple layers of various dielectrics, but in one implementation, the overall thickness is less than approximately 50 nanometers. The capacitance per unit area of the capacitive interface formed depends on the particular dielectric constants κ of the dielectric materials employed in the ultrathin layer and their respective thicknesses. Electrical and grounding connections can be made at the edge of the coupled stack.

公开(公告)号：US09905523B2

公开(公告)日：2018-02-27

申请号：US15203013

申请日：2016-07-06

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Arkalgud R. Sitaram

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L25/065 ,  H01L23/14 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/09 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/53209 ,  H01L24/89 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/08168 ,  H01L2224/08501 ,  H01L2224/73204 ,  H01L2224/80487 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/05442 ,  H01L2924/1304 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: Two microelectronic components (110, 120), e.g. a die and an interposer, are bonded to each other. One of the components' contact pads (110C) include metal, and the other component has silicon (410) which reacts with the metal to form metal silicide (504). Then a hole (510) is made through one of the components to reach the metal silicide and possibly even the unreacted metal (110C) of the other component. The hole is filled with a conductor (130), possibly metal, to provide a conductive via that can be electrically coupled to contact pads (120C.B) attachable to other circuit elements or microelectronic components, e.g. to a printed circuit board.

公开(公告)号：US20170309518A1

公开(公告)日：2017-10-26

申请号：US15649457

申请日：2017-07-13

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Guilian Gao ,  Liang Wang ,  Hong Shen ,  Arkalgud R. Sitaram

IPC: H01L21/82 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31

Abstract: A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.

公开(公告)号：US09769923B2

公开(公告)日：2017-09-19

申请号：US15380172

申请日：2016-12-15

Applicant: Invensas Corporation

Inventor： Bong-Sub Lee ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Liang Wang ,  Laura Wills Mirkarimi ,  Arkalgud R. Sitaram

IPC: H05K13/04 ,  H05K1/09 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11

CPC classification number: H05K1/097 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/112 ,  H05K1/113 ,  H05K1/165 ,  H05K3/188 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/5313 ,  H01L2924/00

Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130′) covered by a conductive coating (130″) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.

公开(公告)号：US20170099733A1

公开(公告)日：2017-04-06

申请号：US15380172

申请日：2016-12-15

Applicant: Invensas Corporation

Inventor： Bong-Sub Lee ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Liang Wang ,  Laura Wills Mirkarimi ,  Arkalgud R. Sitaram

IPC: H05K1/09 ,  H01L21/48 ,  H05K1/11 ,  H01L23/498

CPC classification number: H05K1/097 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/112 ,  H05K1/113 ,  H05K1/165 ,  H05K3/188 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/5313 ,  H01L2924/00

Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130′) covered by a conductive coating (130″) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.

公开(公告)号：US20170092620A1

公开(公告)日：2017-03-30

申请号：US15247705

申请日：2016-08-25

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Arkalgud R. Sitaram

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/311 ,  H01L25/00 ,  H01L21/02

CPC classification number: H01L25/0657 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/31111 ,  H01L23/642 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/27452 ,  H01L2224/27614 ,  H01L2224/29187 ,  H01L2224/32135 ,  H01L2224/83896 ,  H01L2225/06531 ,  H01L2924/01072 ,  H01L2924/0534 ,  H01L2924/05442 ,  H01L2924/30105

Abstract: Capacitive coupling of integrated circuit die components and other conductive areas is provided. Each component to be coupled has a surface that includes at least one conductive area, such as a metal pad or plate. An ultrathin layer of dielectric is formed on at least one surface to be coupled. When the two components, e.g., one from each die, are permanently contacted together, the ultrathin layer of dielectric remains between the two surfaces, forming a capacitor or capacitive interface between the conductive areas of each respective component. The ultrathin layer of dielectric may be composed of multiple layers of various dielectrics, but in one implementation, the overall thickness is less than approximately 50 nanometers. The capacitance per unit area of the capacitive interface formed depends on the particular dielectric constants K of the dielectric materials employed in the ultrathin layer and their respective thicknesses. Electrical and grounding connections can be made at the edge of the coupled stack.

公开(公告)号：US09536862B2

公开(公告)日：2017-01-03

申请号：US14980996

申请日：2015-12-28

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram

IPC: H01L23/48 ,  H01L21/50 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00 ,  H01L21/52 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/52 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/5384 ,  H01L24/09 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/08165 ,  H01L2224/08235 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/8182 ,  H01L2224/85205 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Semiconductor integrated circuits (110) or assemblies are disposed at least partially in cavities between two interposers (120). Conductive vias (204M) pass through at least one of the interposers or at least through the interposer's substrate, and reach a semiconductor integrated circuit or an assembly. Other conductive vias (204M.1) pass at least partially through multiple interposers and are connected to conductive vias that reach, or are capacitively coupled to, a semiconductor IC or an assembly. Other features are also provided.

Abstract translation: 半导体集成电路（110）或组件至少部分地设置在两个插入件（120）之间的空腔中。 导电通孔（204M）通过至少一个插入件或至少穿过插入器的衬底，并到达半导体集成电路或组件。 其他导电通孔（204M.1）至少部分地通过多个插入件并且连接到到达或者电容耦合到半导体IC或组件的导电通孔。 还提供其他功能。