公开(公告)号：US20230411245A1

公开(公告)日：2023-12-21

申请号：US18238726

申请日：2023-08-28

Applicant: Intel Corporation

Inventor： Ravindranath MAHAJAN ,  Debendra MALLIK ,  Sujit SHARAN ,  Digvijay RAORANE

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/34 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/481 ,  H01L21/565 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/34 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/17 ,  H01L24/29 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/73253

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

公开(公告)号：US20230369071A1

公开(公告)日：2023-11-16

申请号：US18226129

申请日：2023-07-25

Applicant: Intel Corporation

Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Bassam M. ZIADEH ,  Yoshihiro TOMITA

IPC: H01L21/56 ,  H01L23/16 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L21/563 ,  H01L23/16 ,  H01L23/562 ,  H01L25/0657 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/81192 ,  H01L2224/92125 ,  H01L2224/48465 ,  H01L2225/06541 ,  H01L2224/13082 ,  H01L2224/73204 ,  H01L2924/1579 ,  H01L2924/3511 ,  H01L2224/81007 ,  H01L2224/14181 ,  H01L2224/0401 ,  H01L2224/97 ,  H01L2224/81191 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16225 ,  H01L2225/06568 ,  H01L2224/32225 ,  H01L2224/83192 ,  H01L24/32 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2225/06513 ,  H01L24/13 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/81203 ,  H01L2224/81211 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2224/81011 ,  H01L24/81 ,  H01L2924/2064 ,  H01L24/83 ,  H01L2224/26175 ,  H01L24/14 ,  H01L24/73 ,  H01L24/16 ,  H01L2924/1434 ,  H01L2225/06517 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/15311

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

公开(公告)号：US20230207475A1

公开(公告)日：2023-06-29

申请号：US17561580

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Xavier F. BRUN ,  Sanka GANESAN ,  Debendra MALLIK

IPC: H01L23/538 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L25/0657 ,  H01L23/5384 ,  H01L23/5386

Abstract: Embodiments disclosed herein include chiplet modules and die modules. In an embodiment, a chiplet module comprises a first chiplet, where the first chiplet comprises a first active surface. In an embodiment the chiplet module further comprises a second chiplet, where the second chiplet comprises a second active surface. In an embodiment, the chiplet module further comprises a hybrid bonding interface between the first chiplet and the second chiplet, where the hybrid bonding interface electrically couples the first chiplet to the second chiplet.

公开(公告)号：US20230134049A1

公开(公告)日：2023-05-04

申请号：US18089227

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Ravindranath MAHAJAN ,  Robert SANKMAN ,  Shawna LIFF ,  Srinivas PIETAMBARAM ,  Bharat PENMECHA

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US20220278032A1

公开(公告)日：2022-09-01

申请号：US17186289

申请日：2021-02-26

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Debendra MALLIK ,  Kristof DARMAWIKARTA ,  Ravindranath V. MAHAJAN ,  Rahul N. MANEPALLI

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538

Abstract: An electronic package includes an interposer having an interposer substrate, a cavity that passes into but not through the interposer substrate, a through interposer via (TIV) within the interposer substrate, and an interposer pad electrically coupled to the TIV. The electronic package includes a nested component in the cavity, wherein the nested component includes a component pad coupled to a through-component via. A core via is beneath the nested component, the core via extending from the nested component through the interposer substrate. A die is coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.

公开(公告)号：US20220155539A1

公开(公告)日：2022-05-19

申请号：US16953146

申请日：2020-11-19

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Brandon C. MARIN ,  Sameer PAITAL ,  Sai VADLAMANI ,  Rahul N. MANEPALLI ,  Xiaoqian LI ,  Suresh V. POTHUKUCHI ,  Sujit SHARAN ,  Arnab SARKAR ,  Omkar KARHADE ,  Nitin DESHPANDE ,  Divya PRATAP ,  Jeremy ECTON ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Zhichao ZHANG ,  Kemal AYGÜN ,  Bai NIE ,  Kristof DARMAWIKARTA ,  James E. JAUSSI ,  Jason M. GAMBA ,  Bryan K. CASPER ,  Gang DUAN ,  Rajesh INTI ,  Mozhgan MANSURI ,  Susheel JADHAV ,  Kenneth BROWN ,  Ankar AGRAWAL ,  Priyanka DOBRIYAL

IPC: G02B6/42

Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

公开(公告)号：US20220115362A1

公开(公告)日：2022-04-14

申请号：US17067069

申请日：2020-10-09

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Ravindranath MAHAJAN ,  Dipankar DAS

IPC: H01L25/16 ,  H01L23/32 ,  H05K7/10 ,  G02B6/42

Abstract: A processor package module comprises a processor-memory stack including one or more compute die stacked and interconnected with a memory stack on a substrate. One or more photonic die is on the substrate to transmit and receive optical I/O, the one or more photonic die connected to the processor-memory stack and connected to external components through a fiber array. The substrate is mounted into a socket housing, such as a land grid array (LGA) socket. An array of processor package modules are interconnected on a processor substrate via fiber arrays and optical connectors to form a processor chip complex.

公开(公告)号：US20220028788A1

公开(公告)日：2022-01-27

申请号：US17492476

申请日：2021-10-01

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Tarek IBRAHIM ,  Kristof DARMAWIKARTA ,  Rahul N. MANEPALLI ,  Debendra MALLIK ,  Robert L. SANKMAN

IPC: H01L23/538 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.

公开(公告)号：US20210043570A1

公开(公告)日：2021-02-11

申请号：US16534027

申请日：2019-08-07

Applicant: Intel Corporation

Inventor： Sanka GANESAN ,  Kevin MCCARTHY ,  Leigh M. TRIBOLET ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Robert L. SANKMAN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge with a hybrid layer on a high-density packaging (HDP) substrate, a plurality of dies over the bridge and the HDP substrate, and a plurality of through mold vias (TMVs) on the HDP substrate. The bridge is coupled between the dies and the HDP substrate. The bridge is directly coupled to two dies of the dies with the hybrid layer, where a top surface of the hybrid layer of the bridge is directly on bottom surfaces of the dies, and where a bottom surface of the bridge is directly on a top surface of the HDP substrate. The TMVs couple the HDP substrate to the dies, and have a thickness that is substantially equal to a thickness of the bridge. The hybrid layer includes conductive pads, surface finish, and/or dielectric.

公开(公告)号：US20200051956A1

公开(公告)日：2020-02-13

申请号：US16100149

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Omkar KARHADE ,  Nitin DESHPANDE ,  Debendra MALLIK

IPC: H01L25/065 ,  H01L23/538

Abstract: A semiconductor package is disclosed. The semiconductor package includes a package substrate, at least one bottom die coupled to the package substrate, at least one interposer coupled to the package substrate and a top die above the at least one bottom die and the at least one interposer and coupled to the at least one bottom die and the at least one interposer. The semiconductor package also includes a plurality of pillars that connect the top die to the package substrate through the at least one interposer.