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    CREST FACTOR REDUCTION USING PEAK CANCELLATION WITHOUT PEAK REGROWTH
    31.
    发明公开
    CREST FACTOR REDUCTION USING PEAK CANCELLATION WITHOUT PEAK REGROWTH 审中-公开

    公开(公告)号：US20240004957A1

    公开(公告)日：2024-01-04

    申请号：US17854095

    申请日：2022-06-30

    Applicant: Intel Corporation

    Inventor： Sunitha Motipalli ,  Kameran Azadet ,  Albert Molina ,  Joseph Othmer ,  Kannan Rajamani

    IPC: G06K9/00

    CPC classification number: G06K9/0053 ,  G06K9/0055

    Abstract: Techniques are disclosed for the use of Crest Factor Reduction (CFR) algorithm that performs oversampling of an input signal and a cancellation pulse, and detects a set of peak samples in the upsampled input signal that exceed a predetermined threshold value. The peak samples are clustered such that a subset of the oversampled signal peaks are used to compute gain factors for the generation of a scaled truncated upsampled cancellation pulse. Several scaled truncated upsampled cancellation pulses are applied in parallel to perform peak cancellation of the highest peak in each cluster as part of an initial peak cancellation process. Any remaining peaks are canceled by iterative gain factors computation process. A final cancellation pulse is then generated by multiplying a cancellation pulse by the computed gain factors.

    Digital-to-analog converter
    33.
    发明授权
    Digital-to-analog converter 有权

    公开(公告)号：US11171663B2

    公开(公告)日：2021-11-09

    申请号：US16833729

    申请日：2020-03-30

    Applicant: Intel Corporation

    Inventor： Daniel Gruber ,  Ramon Sanchez ,  Kameran Azadet ,  Martin Clara

    IPC: H03M1/66 ,  H01P5/10 ,  H04B1/04 ,  H01F19/04 ,  H03H7/38 ,  H03H7/42

    Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a first plurality of digital-to-analog converter cells configured to generate a first analog signal. Further, digital-to-analog converter includes a second plurality of digital-to-analog converter cells configured to generate a second analog signal. The first analog signal and the second analog signal form a differential signal pair. Further, the digital-to-analog converter includes a transmission line transformer comprising a first input node coupled to the first plurality of digital-to-analog converter cells, a second input node coupled to the second plurality of digital-to-analog converter cells, and a first output node. The transmission line transformer is configured to present a first impedance at the first and second input nodes and to present a second impedance at the first output node.

    Digital-to-analog conversion system
    34.
    发明授权
    Digital-to-analog conversion system 有权

    公开(公告)号：US10715185B1

    公开(公告)日：2020-07-14

    申请号：US16369317

    申请日：2019-03-29

    Applicant: Intel Corporation

    Inventor： Daniel Gruber ,  Ramon Sanchez ,  Kameran Azadet ,  Martin Clara

    IPC: H04B1/00 ,  H04B1/04 ,  H03M1/66 ,  H04B1/10

    Abstract: A digital-to-analog conversion system is provided. The digital-to-analog conversion system includes a digital-to-analog converter configured to receive a pre-distorted digital signal from a digital circuit, and to generate an analog signal based on the pre-distorted digital signal. Further, the digital-to-analog conversion system includes a feedback loop for providing a digital feedback signal to the digital circuit. The feedback loop includes an analog-to-digital converter configured to generate the digital feedback signal based on the analog signal, and wherein a sample rate of the analog-to-digital converter is lower than a sample rate of the digital-to-analog converter.

    Digital-to-analog converter
    35.
    发明授权
    Digital-to-analog converter 有权

    公开(公告)号：US10608661B1

    公开(公告)日：2020-03-31

    申请号：US16369262

    申请日：2019-03-29

    Applicant: Intel Corporation

    Inventor： Daniel Gruber ,  Ramon Sanchez ,  Kameran Azadet ,  Martin Clara

    IPC: H03M1/66 ,  H01P5/10 ,  H04B1/04 ,  H01F19/04 ,  H03H7/38 ,  H03H7/42

    Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a first plurality of digital-to-analog converter cells configured to generate a first analog signal. Further, digital-to-analog converter includes a second plurality of digital-to-analog converter cells configured to generate a second analog signal. The first analog signal and the second analog signal form a differential signal pair. Further, the digital-to-analog converter includes a transmission line transformer comprising a first input node coupled to the first plurality of digital-to-analog converter cells, a second input node coupled to the second plurality of digital-to-analog converter cells, and a first output node. The transmission line transformer is configured to present a first impedance at the first and second input nodes and to present a second impedance at the first output node.

    Vector processor having instruction set with sliding window non-linear convolutional function
    39.
    发明授权
    Vector processor having instruction set with sliding window non-linear convolutional function 有权
    矢量处理器具有滑动窗非线性卷积函数的指令集

    公开(公告)号：US09363068B2

    公开(公告)日：2016-06-07

    申请号：US14168615

    申请日：2014-01-30

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Joseph Williams ,  Meng-Lin Yu

    IPC: G06F17/15 ,  H04L5/14 ,  H04L25/08 ,  G06F17/50 ,  H04B1/62 ,  H04L1/00 ,  H04B1/04 ,  G06F9/30 ,  H04L25/03 ,  H04L27/36 ,  H04J11/00 ,  H04B1/525

    CPC classification number: H04L5/1461 ,  G06F9/30036 ,  G06F17/15 ,  G06F17/50 ,  G06F17/5009 ,  H04B1/0475 ,  H04B1/525 ,  H04B1/62 ,  H04B2001/0425 ,  H04J11/004 ,  H04L1/0043 ,  H04L25/03012 ,  H04L25/03343 ,  H04L25/08 ,  H04L27/367 ,  H04L27/368

    Abstract: A processor is provided having an instruction set with a sliding window non-linear convolution function. A processor obtains a software instruction that performs a non-linear convolution function for a plurality of input delayed signal samples. In response to the software instruction for the non-linear convolution function, the processor generates a weighted sum of two or more of the input delayed signal samples, wherein the weighted sum comprises a plurality of variable coefficients defined as a sum of one or more non-linear functions of a magnitude of the input delayed signal samples; and repeats the generating step for at least one time-shifted version of the input delayed signal samples to compute a plurality of consecutive outputs. The software instruction for the non-linear convolution function is optionally part of an instruction set of the processor. The non-linear convolution function can model a non-linear system with memory, such as a power amplifier model and/or a digital pre-distortion function.

    Abstract translation: 提供具有具有滑动窗非线性卷积函数的指令集的处理器。 处理器获得对多个输入延迟信号样本执行非线性卷积函数的软件指令。 响应于用于非线性卷积函数的软件指令，处理器生成两个或更多个输入延迟信号样本的加权和，其中加权和包括被定义为一个或多个非线性卷积的和的多个可变系数， 输入延迟信号采样幅度的线性函数; 并重复所述生成步骤，用于输入延迟信号采样的至少一个时移版本，以计算多个连续输出。 用于非线性卷积函数的软件指令可选地是处理器的指令集的一部分。 非线性卷积函数可以对具有存储器的非线性系统进行建模，例如功率放大器模型和/或数字预失真功能。

    Non-linear modeling of a physical system using look-up table with polynomial interpolation
    40.
    发明授权
    Non-linear modeling of a physical system using look-up table with polynomial interpolation 有权
    使用多项式插值的查找表对物理系统进行非线性建模

    公开(公告)号：US09225501B2

    公开(公告)日：2015-12-29

    申请号：US14230622

    申请日：2014-03-31

    Applicant: Intel Corporation

    Inventor： Kameran Azadet

    IPC: H04L25/03 ,  H04L5/14 ,  H04L25/08 ,  G06F17/50 ,  H04B1/62 ,  H04L1/00 ,  H04B1/04 ,  G06F17/15 ,  H04L27/36 ,  H04J11/00 ,  H04B1/525

    CPC classification number: H04L5/1461 ,  G06F9/30036 ,  G06F17/15 ,  G06F17/50 ,  G06F17/5009 ,  H04B1/0475 ,  H04B1/525 ,  H04B1/62 ,  H04B2001/0425 ,  H04J11/004 ,  H04L1/0043 ,  H04L25/03012 ,  H04L25/03343 ,  H04L25/08 ,  H04L27/367 ,  H04L27/368

    Abstract: Methods and apparatus are provided for non-linear modeling of a physical system using look-up tables with polynomial interpolation. A non-linear function is evaluated for a complex input value by obtaining at least one look-up table with polynomial interpolation that represents the non-linear function, wherein entries in the look-up table comprise polynomial coefficients of at least degree two for different segments of the non-linear function; obtaining a point from the look-up table that is near a magnitude of the complex input value; and generating a complex output value by evaluating the polynomial coefficients at the point to perform a Taylor Series expansion from said point. The non-linear function characterizes, for example, a power amplifier or an inverse of a power amplifier and the look-up tables can be used, for example, to implement digital pre-distortion.

    Abstract translation: 提供了使用具有多项式插值的查找表对物理系统进行非线性建模的方法和装置。 通过获得表示非线性函数的多项式插值的至少一个查找表，对复数输入值评估非线性函数，其中查找表中的条目包括至少二等于不同的多项式系数 段的非线性函数; 从所述查找表获得接近复数输入值的大小的点; 以及通过评估从所述点执行泰勒级数展开的点处的多项式系数来产生复数输出值。 非线性功能表征例如功率放大器或功率放大器的反相，并且可以使用查找表来实现数字预失真。

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