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    Integrated circuit structures for increasing resistance to single event upset
    31.
    发明申请
    Integrated circuit structures for increasing resistance to single event upset 有权
    集成电路结构，增加对单一事件的不耐烦

    公开(公告)号：US20060001045A1

    公开(公告)日：2006-01-05

    申请号：US10883091

    申请日：2004-07-01

    申请人： Lakhbeer Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

    发明人： Lakhbeer Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

    IPC分类号： H01L29/739 ,  H01L27/10 ,  G11C16/04 ,  G11C11/34

    CPC分类号： G11C11/412 ,  H01L27/0207 ,  H01L27/11807

    摘要： A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

    摘要翻译： 用于现场可编程门阵列（“FPGA”）集成电路（“IC”）器件的配置存储单元（“CRAM”）被赋予增加的对单一事件不正常（“SEU”）的阻力。 CRAM的输入节点的栅极结构的一部分相对于栅极结构的其余部分的标称尺寸增大。 放大栅极结构的一部分位于与IC的N阱区电容性相邻的位置，另一部分位于与IC的P阱区电容相邻的位置。 这种布置使得输入节点增加了抵抗SEU的电容，而与输入节点的逻辑电平无关。 本发明也可应用于任何类型的存储器单元的任何节点，其对期望增加的对SEU的抗性。

    Electrostatic discharge protection circuit
    33.
    发明申请
    Electrostatic discharge protection circuit 有权
    静电放电保护电路

    公开(公告)号：US20050270714A1

    公开(公告)日：2005-12-08

    申请号：US10861604

    申请日：2004-06-03

    申请人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie Tran

    发明人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie Tran

    IPC分类号： H01L27/02 ,  H02H9/00

    CPC分类号： H01L27/0266 ,  H01L27/0251

    摘要： Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.

    摘要翻译： 提供具有诸如可编程多晶硅保险丝等敏感电路的集成电路。 提供静电放电（ESD）保护电路，防止在存在静电放电事件时敏感电路的损坏或不期望的编程。 静电放电保护电路可以具有电源ESD器件，其将敏感电路两端的电压电平限制到最大电压，并且当暴露于ESD信号时，其将电流从敏感电路吸取。 静电放电保护电路还可以具有ESD余量电路，当在敏感电路上施加最大电压时，该余量电路有助于防止电流流经敏感电路。

    Method of forming a semiconductor structure having MOS, bipolar, and varactor devices
    34.
    发明授权
    Method of forming a semiconductor structure having MOS, bipolar, and varactor devices 失效
    形成具有MOS，双极和变容二极管器件的半导体结构的方法

    公开(公告)号：US5405790A

    公开(公告)日：1995-04-11

    申请号：US155882

    申请日：1993-11-23

    申请人： Irfan Rahim ,  Bor-Yuan C. Hwang ,  Julio Costa

    发明人： Irfan Rahim ,  Bor-Yuan C. Hwang ,  Julio Costa

    IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L29/93 ,  H01L21/265

    CPC分类号： H01L27/0635 ,  H01L21/8249 ,  Y10S148/009

    摘要： A varactor (10, 115, 122) is formed using a BICMOS process flow. An N well (28) of a varactor region (13) is formed in an epitaxial layer (22) by doping the epitaxial layer (22) with an N type dopant. A cathode region (55, 132) is formed in the N well (28) by further doping the N well (28) with the N type dopant. Cathode electrodes (91, 114) are formed by patterning a layer of polysilicon (62, 86) over the epitaxial layer (22). Subsequently, the cathode electrodes (91, 114) are doped with an N type dopant. A region adjacent the cathode region (55, 132) is doped to form a lightly doped region (103, 117). The lightly doped region (103, 117) is doped with a P type dopant to form an anode region (109, 119).

    摘要翻译： 使用BICMOS工艺流程形成变容二极管（10,115,122）。 通过用N型掺杂剂掺杂外延层（22），在外延层（22）中形成变容二极管区域（13）的N阱（28）。 通过用N型掺杂剂进一步掺杂N阱（28），在N阱（28）中形成阴极区（55,132）。 通过在外延层（22）上图案化多晶硅层（62,86）来形成阴极电极（91,114）。 随后，阴极电极（91,114）掺杂有N型掺杂剂。 与阴极区域（55,132）相邻的区域被掺杂以形成轻掺杂区域（103,117）。 轻掺杂区域（103,117）掺杂有P型掺杂剂以形成阳极区域（109,119）。

    Memory elements with relay devices
    35.
    发明授权
    Memory elements with relay devices 有权
    具有中继设备的存储器元件

    公开(公告)号：US08611137B2

    公开(公告)日：2013-12-17

    申请号：US13304226

    申请日：2011-11-23

    申请人： Lin-Shih Liu ,  Mark T. Chan ,  Yanzhong Xu ,  Irfan Rahim ,  Jeffrey T. Watt

    发明人： Lin-Shih Liu ,  Mark T. Chan ,  Yanzhong Xu ,  Irfan Rahim ,  Jeffrey T. Watt

    IPC分类号： G11C11/00

    CPC分类号： G11C11/52 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  H01H1/0094 ,  H01H1/20 ,  H01H59/0009 ,  H01L27/101 ,  H01L27/11

    摘要： Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity.

    摘要翻译： 提供具有存储元件的集成电路。 集成电路可以包括形成在具有互补金属氧化物半导体（CMOS）器件的第一部分中的逻辑电路，并且可以包括形成在具有纳米机电（NEM）器件的第二部分中的存储器元件和相关联的存储器电路的至少一部分， 中继设备 NEM和CMOS器件可以通过介电堆叠中的通孔互连。 第一和第二部分中的装置可以接收相应的电源电压。 在一个合适的布置中，存储器元件可以包括提供非易失性存储特性和软错误失真（SEU）抗扰性的两个继电器开关。 在另一种合适的布置中，存储元件可以包括第一和第二交叉耦合反相电路。 第一反相电路可以包括继电器开关，而第二反相电路仅包括CMOS晶体管。 以这种方式配置的存储器元件可用于提供易失性存储特性和SEU抗扰度。

    Integrated circuit well isolation structures
    36.
    发明授权
    Integrated circuit well isolation structures 有权
    集成电路阱隔离结构

    公开(公告)号：US07902611B1

    公开(公告)日：2011-03-08

    申请号：US11998016

    申请日：2007-11-27

    申请人： Irfan Rahim ,  Bradley Jensen ,  Peter J. McElheny

    发明人： Irfan Rahim ,  Bradley Jensen ,  Peter J. McElheny

    IPC分类号： H01L21/70 ,  H01L23/52 ,  H01L29/00

    CPC分类号： H01L27/0928 ,  H01L21/76224 ,  H01L21/765 ,  H01L21/823878 ,  H01L21/823892

    摘要： An integrated circuit is provided with transistor body regions that may be independently biased. Some of the bodies may be forward body biased to lower threshold voltages and increase transistor switching speed. Some of the bodies may be reverse body biased to increase threshold voltages and decrease leakage current. The integrated circuit may be formed on a silicon substrate. Body bias isolation structures may be formed in the silicon substrate to isolate the bodies from each other. Body bias isolation structures may be formed from shallow trench isolation trenches. Doped regions may be formed at the bottom of the trenches using ion implantation. Oxide may be used to fill the trenches above the doped region. A deep well may be formed under the body regions. The deep well may contact the doped regions that are formed at the bottom of the trenches.

    摘要翻译： 集成电路设置有可独立偏置的晶体管本体区域。 一些物体可能被向前偏置，以降低阈值电压并增加晶体管切换速度。 一些物体可能被反向体偏置以增加阈值电压并减小漏电流。 集成电路可以形成在硅衬底上。 可以在硅衬底中形成体偏置隔离结构以将体彼此隔离。 体偏置隔离结构可以由浅沟槽隔离沟槽形成。 可以使用离子注入在沟槽的底部形成掺杂区域。 氧化物可用于填充掺杂区域上方的沟槽。 可以在身体区域下方形成深井。 深阱可以接触形成在沟槽底部的掺杂区域。

    On-chip voltage regulator using feedback on process/product parameters
    37.
    发明授权
    On-chip voltage regulator using feedback on process/product parameters 失效
    片上电压调节器，使用过程/产品参数反馈

    公开(公告)号：US07639033B2

    公开(公告)日：2009-12-29

    申请号：US11638846

    申请日：2006-12-13

    申请人： Irfan Rahim ,  Peter McElheny ,  John Costello

    发明人： Irfan Rahim ,  Peter McElheny ,  John Costello

    IPC分类号： G01R31/00 ,  G01R31/28

    CPC分类号： G11C5/147 ,  H03K19/177

    摘要： The present invention optimizes the performance of integrated circuits by adjusting the circuit operating voltage using feedback on process/product parameters. To determine a desired value for the operating voltage of an integrated circuit, a preferred embodiment provides for on-wafer probing of one or more reference circuit structures to measure at least one electrical or operational parameter of the one or more reference circuit structures; determining an adjusted value for the operating voltage based on the measured parameter; and establishing the adjusted value as the desired value for the operating voltage. The reference circuit structures may comprise process control monitor structures or structures in other integrated circuits fabricated in the same production run. In an alternative embodiment, the one or more parameters are directly measured from the integrated circuit whose operating voltage is being adjusted.

    摘要翻译： 本发明通过使用对过程/产品参数的反馈来调节电路工作电压来优化集成电路的性能。 为了确定集成电路的工作电压的期望值，优选实施例提供一个或多个参考电路结构的片上探测，以测量一个或多个参考电路结构的至少一个电或操作参数; 基于所测量的参数确定所述工作电压的调整值; 并将调整后的值建立为工作电压的期望值。 参考电路结构可以包括在相同生产运行中制造的其它集成电路中的过程控制监视器结构或结构。 在替代实施例中，一个或多个参数是直接从其工作电压正被调整的集成电路测量的。

    Integrated circuit structures for increasing resistance to single event upset
    40.
    发明授权
    Integrated circuit structures for increasing resistance to single event upset 有权

    公开(公告)号：US07465971B2

    公开(公告)日：2008-12-16

    申请号：US11951122

    申请日：2007-12-05

    申请人： Lakhbeer S. Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

    发明人： Lakhbeer S. Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

    IPC分类号： H01L29/94

    CPC分类号： G11C11/412 ,  H01L27/0207 ,  H01L27/11807

    摘要： A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.