公开(公告)号：US5301118A

公开(公告)日：1994-04-05

申请号：US793981

申请日：1991-11-18

申请人： Howard L. Heck ,  John S. Kresge

发明人： Howard L. Heck ,  John S. Kresge

IPC分类号： B23P21/00 ,  G06F17/18 ,  G06F17/50 ,  G06F19/00 ,  G06F15/46

CPC分类号： G06F17/18 ,  G06F17/5009 ,  G06F2217/10

摘要： A two-stage Monte Carlo method of tolerancing components of an assembly is provided. Statistical measures of component features are not time invariant, but change over a production run. That is, the mean value of component feature measures and the standard distribution of the component feature measures about the time dependent mean are not invariant over a production run, but shift with time and throughput. According to the invention, these "shifted" or "adjusted" parameters are utilized in a Monte Carlo simulation to determine discrete values for the individual points of each output distribution, x(i), y(i), z(i). The individual points of the output distributions, x(i), y(i), z(i), are combined in a second Monte Carlo simulation step for individual assembly final fit F(x(i), y(i), z(i)). The statistics of the individual assembly final fits are then compared to manufacturing specifications.

摘要翻译： 提供了一种用于组装组件公差的两阶段蒙特卡罗方法。 组件特征的统计测量不是时间不变的，而是改变生产运行。 也就是说，组件特征量度的平均值和关于时间依赖平均值的组件特征量度的标准分布在生产运行中不是不变的，而是随时间和吞吐量而变化。 根据本发明，在蒙特卡罗模拟中使用这些“移位”或“调整”参数来确定每个输出分布x（i），y（i），z（i）的各个点的离散值。 输出分布x（i），y（i），z（i）的各个点在用于单独组合最终拟合F（x（i），y（i），z）的第二蒙特卡罗模拟步骤中组合 （一世））。 然后将各组装最终配合的统计数据与制造规范进行比较。

公开(公告)号：US06958106B2

公开(公告)日：2005-10-25

申请号：US10409066

申请日：2003-04-09

申请人： Timothy E. Antesberger ,  John S. Kresge

发明人： Timothy E. Antesberger ,  John S. Kresge

IPC分类号： H05K3/34 ,  B31D1/02 ,  H01L21/48 ,  H01L21/60 ,  H01L23/36 ,  H05K3/00 ,  H05K3/36 ,  H05K3/38 ,  B32B31/08 ,  B32B31/18

CPC分类号： B31D1/026 ,  H01L21/4882 ,  H01L2224/73253 ,  H01L2924/01057 ,  H01L2924/01078 ,  H05K3/0058 ,  H05K3/386 ,  Y10T156/1064

摘要： A method of removing selected portions of material from a base material using a plurality of different depth cuts (e.g., using laser cutting) such that apertured sections (or segments) are expeditiously removed for eventual use with another component or otherwise. In one example, the segmented section so removed can be used to bond various elements of an electronic package which in turn can then be positioned and used within an information handling system such as a computer, server, mainframe, etc.

公开(公告)号：US06753612B2

公开(公告)日：2004-06-22

申请号：US09827014

申请日：2001-04-05

申请人： Sylvia Adae-Amoakoh ,  John S. Kresge ,  Voya R. Markovich ,  Thurston B. Youngs, Jr.

发明人： Sylvia Adae-Amoakoh ,  John S. Kresge ,  Voya R. Markovich ,  Thurston B. Youngs, Jr.

IPC分类号： H01L2940

CPC分类号： H05K3/4069 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/113 ,  H05K3/061 ,  H05K3/062 ,  H05K3/247 ,  H05K3/3484 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0305 ,  H05K2201/035 ,  H01L2224/0401

摘要： A flip-chip joinable substrate having non-plated-on contact pads. The substrate has an external metal foil layer upon a dielectric layer upon a patterned internal metal layer having an internal contact area. An area of the external metal foil layer above the internal contact area is selected. A microvia cavity extending to the internal contact area is perforated centrally within the selected area and is filled with a mass of conductive paste forming an external contact pad. The external contact pad is used as an etch mask for removing the adjacent external metal foil.

摘要翻译： 具有非电镀接触焊盘的倒装芯片可连接衬底。 衬底在具有内部接触面积的图案化内部金属层上的介电层上具有外部金属箔层。 选择内部接触区域上方的外部金属箔层的区域。 延伸到内部接触区域的微孔腔在所选择的区域内中心穿孔，并且填充有形成外部接触焊盘的导电浆料块。 外部接触焊盘用作蚀刻掩模以去除相邻的外部金属箔。

公开(公告)号：US06203652B1

公开(公告)日：2001-03-20

申请号：US09345326

申请日：1999-06-30

申请人： Frank D. Egitto ,  John S. Kresge

发明人： Frank D. Egitto ,  John S. Kresge

IPC分类号： B32B3118

CPC分类号： H05K3/0032 ,  H05K3/0035 ,  H05K2203/1383 ,  Y10T29/49165 ,  Y10T156/1057

摘要： A method of forming a via in a substrate is provided. The method generally includes laminating a support to the substrate, forming the via in the substrate, and then stripping the support from the substrate. The support is preferably a photoresist that collects any debris generated by the via formation so that the debris is removed from the via and substrate surface as the photoresist support is stripped.

摘要翻译： 提供了在基板中形成通孔的方法。 该方法通常包括将支撑物层压到基底上，在基底中形成通孔，然后从基底剥离载体。 载体优选是光致抗蚀剂，其收集由通孔形成物产生的任何碎屑，使得当光致抗蚀剂载体被剥离时，碎屑从通孔和基底表面除去。

公开(公告)号：US6073344A

公开(公告)日：2000-06-13

申请号：US239384

申请日：1999-01-28

申请人： Robert M. Japp ,  John S. Kresge

发明人： Robert M. Japp ,  John S. Kresge

IPC分类号： H05K3/02 ,  H05K3/18 ,  H05K3/40 ,  H05K3/36

CPC分类号： H05K3/403 ,  H05K3/027 ,  H05K2201/09645 ,  H05K2203/107 ,  H05K3/185 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49165

摘要： A method for generating multiple conductor segments within a plated through hole of a printed circuit board. The method utilizes laser light to define the segmented surfaces bounding a hole in a circuit board. Two embodiments of this method are a subtractive process and an additive process. The subtractive process starts with a plated through hole and uses a laser to removes vertical strips of the PTH conductive lining to form the multiple conductive segments. The additive process applies a seeding material to a bare hole in a circuit board, removes vertical strips of the seeding material via laser scanning, and applies an electrically conductive material to the seeded surfaces to form the multiple conductive segments.

摘要翻译： 一种用于在印刷电路板的电镀通孔内产生多个导体段的方法。 该方法利用激光来定义界定电路板中的孔的分段表面。 该方法的两个实施例是减法处理和加法处理。 减法过程从电镀通孔开始，并使用激光去除PTH导电衬里的垂直条，以形成多个导电段。 添加方法将种子材料施加到电路板中的裸露孔中，通过激光扫描去除接种材料的垂直条带，并将导电材料施加到种子表面以形成多个导电段。

公开(公告)号：US5956235A

公开(公告)日：1999-09-21

申请号：US22848

申请日：1998-02-12

申请人： John S. Kresge ,  Robin A. Susko ,  James W. Wilson

发明人： John S. Kresge ,  Robin A. Susko ,  James W. Wilson

IPC分类号： H01R13/24 ,  H05K1/11 ,  H05K1/18 ,  H05K3/34 ,  H01R9/00

CPC分类号： H01R13/2414 ,  H01R12/52 ,  H05K3/3436 ,  H01L2224/16237 ,  H05K2201/0212 ,  Y02P70/613

摘要： A flexible interconnect for flexibly connecting an integrated circuit chip to a substrate. The flexible interconnect includes a flexible core, formed of a polymeric material, fully covered by a layer of an electrically conductive metal. A layer of a compliant material is provided beneath the input/output pad of the substrate and/or integrated circuit chip to reduce mechanical stresses on the flexible interconnect. The substrate and integrated circuit chip may include depressions to receive ends of the flexible interconnect. In one embodiment, the flexible interconnect may be tubular in shape and positioned on a protrusion formed on the substrate.

摘要翻译： 用于将集成电路芯片灵活连接到基板的柔性互连。 柔性互连件包括由聚合材料形成的柔性芯，其完全由导电金属层覆盖。 在衬底和/或集成电路芯片的输入/输出焊盘下方提供柔性材料层，以减少柔性互连上的机械应力。 衬底和集成电路芯片可以包括凹陷以接收柔性互连的端部。 在一个实施例中，柔性互连可以是管状形状并且定位在形成在基板上的突起上。

公开(公告)号：US5384690A

公开(公告)日：1995-01-24

申请号：US97544

申请日：1993-07-27

申请人： Charles R. Davis ,  Thomas P. Duffy ,  Steven L. Hanakovic ,  Howard L. Heck ,  John T. Kolias ,  John S. Kresge ,  David N. Light ,  Ajit K. Trivedi

发明人： Charles R. Davis ,  Thomas P. Duffy ,  Steven L. Hanakovic ,  Howard L. Heck ,  John T. Kolias ,  John S. Kresge ,  David N. Light ,  Ajit K. Trivedi

IPC分类号： H01R4/26 ,  H01R4/58 ,  H01R12/61 ,  H01R13/66 ,  H05K1/00 ,  H05K1/03 ,  H05K1/14 ,  H05K3/00 ,  H05K3/32 ,  H05K3/46 ,  H01R23/68

CPC分类号： H05K3/4635 ,  H01R12/613 ,  H01R13/665 ,  H05K3/462 ,  H01R4/26 ,  H01R4/58 ,  H05K1/0373 ,  H05K1/0393 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/09109 ,  H05K2201/09536 ,  H05K2201/10159 ,  H05K3/328 ,  H05K3/4623 ,  H05K3/4641 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49179 ,  Y10T428/24917

摘要： Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate. Lamination of the individual subassemblies is accomplished with a low melting adhesive that is chemical compatible with (bondable to) the perfluorocarbon polymer between the subassemblies in the regions intended to be laminated, and, optionally, a high melting mask that is chemically incompatible with (not bondable to) the perfluorocarbon polymer between the subassemblies in the regions not intended to be laminated. The subassembly stack is heated to selectively effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.

摘要翻译： 公开了一种并行处理器封装结构和用于制造该结构的方法。 单独的逻辑和存储器元件在印刷电路卡上。 这些印刷电路板和卡依次安装在或连接到从电路化的柔性基板的层叠体向外延伸的电路化柔性基板上。 通过在层压板中实现的开关结构来提供互通。 印刷电路卡安装在或连接到多个电路化的柔性基板上，在电路化柔性电路的每一端具有一个印刷电路卡。 电路化的柔性基板通过中央层压体部分连接分开的印刷电路板和卡。 该层压部分为处理器间，存储器间，处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。 作为逻辑芯片或存储器芯片的数据线，地址线和控制线的平面电路在通过电路化的柔性连接的各个印刷电路板和卡上，并且通过Z轴与其它柔性层通信， 轴向电路（通孔和通孔）。 各个子组件的层压是通过与要层压的区域中的子组件之间的全氟化碳聚合物化学相容（可粘合）化学相容的低熔点粘合剂，以及任选的与化学不相容的高熔点掩模 可粘合到）在不想层压的区域中的子组件之间的全氟化碳聚合物。 加热组件叠层以选择性地在要层压的区域中进行粘合和层压，同时避免在不想层压的区域中层压。