公开(公告)号：US20170186676A1

公开(公告)日：2017-06-29

申请号：US15460583

申请日：2017-03-16

Applicant: MEDIATEK, INC.

Inventor： Wen-Sung HSU ,  Tzu-Hung LIN ,  Ta-Jen YU

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate having a die attach surface. A conductive trace is disposed on the substrate, wherein the conductive trace is elongated and carries a signal or a ground across at least a portion of the substrate. A die is mounted on the die attach surface of the substrate via a conductive pillar bump, the conductive pillar bump being rounded and elongated such that the conductive pillar bump extends along a length of the conductive trace and contacts the conductive trace at an end or at an intermediate portion thereof. The die further includes a metal pad electrically coupling to the conductive pillar bump, wherein the metal pad has a first edge and a second edge substantially vertical to the first edge, and wherein the first edge is not adjacent to the second edge.

公开(公告)号：US20160358877A1

公开(公告)日：2016-12-08

申请号：US15238454

申请日：2016-08-16

Applicant: MediaTek Inc.

Inventor： Che-Ya CHOU ,  Wen-Sung HSU ,  Nan-Cheng CHEN

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/367 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/16 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/12042 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/0376 ,  H05K2201/09472 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor device bonded to a base through a first conductive structure. The semiconductor device includes a carrier substrate including a conductive trace. A portion of the conductive trace is elongated. The semiconductor device also includes a second conductive structure above the carrier substrate. A portion of the second conductive structure is in contact with the portion of the conductive trace. The semiconductor device further includes a semiconductor body mounted above the conductive trace. The semiconductor body is connected to the second conductive structure.

Abstract translation: 提供半导体封装。 半导体封装包括通过第一导电结构结合到基底的半导体器件。 半导体器件包括包括导电迹线的载体衬底。 导电迹线的一部分是细长的。 半导体器件还包括载体衬底上方的第二导电结构。 第二导电结构的一部分与导电迹线的部分接触。 半导体器件还包括安装在导电迹线上方的半导体本体。 半导体本体连接到第二导电结构。

公开(公告)号：US20160219714A1

公开(公告)日：2016-07-28

申请号：US14602539

申请日：2015-01-22

Applicant: MediaTek Inc.

Inventor： Wen-Sung HSU ,  Ta-Jen YU

IPC: H05K1/18 ,  H01L21/48 ,  H05K3/00 ,  H05K3/32 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5384 ,  H01L2224/16227 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/205 ,  H01L2924/00012 ,  H01L2924/0001

Abstract: A package substrate is provided. The package substrate includes: a dielectric layer; a passive component embedded in the dielectric layer and contacting the dielectric layer; and a circuit layer embedded in the dielectric layer and having a first surface aligned with a second surface of the dielectric layer.

Abstract translation: 提供封装基板。 封装基板包括：电介质层; 嵌入在介电层中并与电介质层接触的无源元件; 以及电介质层，其电介质层具有与介电层的第二表面对准的第一表面。

公开(公告)号：US20160172292A1

公开(公告)日：2016-06-16

申请号：US14921015

申请日：2015-10-23

Applicant: MediaTek Inc.

Inventor： Wen-Sung HSU ,  Shih-Chin LIN

IPC: H01L23/498 ,  H01L23/31

CPC classification number: H01L23/3114 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a substrate structure having a cavity. A bottom surface of the cavity serves as a die-attach surface of the substrate structure. A semiconductor die is disposed in the cavity and mounted on the die-attach surface. A sidewall of the cavity is separated from the semiconductor die. An interposer is disposed on the substrate structure, covering the cavity.

Abstract translation: 本发明提供一种半导体封装组件。 半导体封装组件包括具有空腔的衬底结构。 腔的底表面用作衬底结构的管芯附着表面。 半导体管芯设置在空腔中并安装在管芯附着表面上。 空腔的侧壁与半导体管芯分离。 插入器设置在衬底结构上，覆盖空腔。

公开(公告)号：US20160153922A1

公开(公告)日：2016-06-02

申请号：US14951698

申请日：2015-11-25

Applicant: MediaTek Inc.

Inventor： Yu-Min LEE ,  Chi-Wen PAN ,  Hung-Wen CHIOU ,  Tai-Yu CHEN ,  Tao CHENG ,  Wen-Sung HSU ,  Sheng-Liang LI

IPC: G01N25/18

CPC classification number: G01N25/18 ,  G01N2033/0078 ,  G01N2033/0095 ,  G06F17/5009 ,  G06F2217/16

Abstract: A computer system and a method for adaptive thermal resistance-capacitance (RC) network analysis of a semiconductor device for use in a portable device are provided. The method includes the steps of: receiving a device input file and a plurality of specific effective heat transfer coefficients (HTCs) associated with the portable device; repeatedly performing a thermal analysis of the portable device based on the device input file and a current effective HTC to estimate a target die temperature of the semiconductor device; calculating a target effective HTC based on the device input file and the target die temperature; and updating the current effective HTC with the target effective HTC; and generating an output file recording the target die temperature of the semiconductor device.

Abstract translation: 提供了一种用于便携式设备的半导体器件的计算机系统和用于自适应热电阻 - 电容（RC）网络分析的方法。 该方法包括以下步骤：接收与便携式设备相关联的设备输入文件和多个特定有效传热系数（HTC）; 基于设备输入文件和当前有效HTC重复执行便携式设备的热分析以估计半导体器件的目标管芯温度; 基于设备输入文件和目标模具温度计算目标有效HTC; 并用目标有效HTC更新当前有效的HTC; 以及生成记录半导体器件的目标管芯温度的输出文件。

公开(公告)号：US20160111358A1

公开(公告)日：2016-04-21

申请号：US14980445

申请日：2015-12-28

Applicant: MediaTek Inc.

Inventor： Wen-Sung HSU ,  Tzu-Hung LIN ,  Ta-Jen YU

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate. First and second conductive traces are disposed on the substrate. A conductive pillar bump is disposed on the second conductive trace, and a first conductive structure is disposed between the second conductive trace and the conductive pillar bump or between the second conductive trace and the substrate. A semiconductor die is disposed over the first conductive trace, wherein the conductive pillar bump connects to the semiconductor die.

Abstract translation: 提供半导体封装。 在一种配置中，半导体封装包括衬底。 第一和第二导电迹线设置在基板上。 导电柱突起设置在第二导电迹线上，并且第一导电结构设置在第二导电迹线和导电柱突起之间或第二导电迹线和基底之间。 半导体管芯设置在第一导电迹线上，其中导电柱凸块连接到半导体管芯。

公开(公告)号：US20150087115A1

公开(公告)日：2015-03-26

申请号：US14556542

申请日：2014-12-01

Applicant: MediaTek Inc.

Inventor： Wen-Sung HSU ,  Ming-Chieh LIN ,  Ta-Jen YU

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L21/4828 ,  H01L21/481 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11912 ,  H01L2224/16238 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8146 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01109 ,  H01L2924/012

Abstract: According to an embodiment of the present invention, a method for forming a chip package is provided. The method includes: providing a conducting plate, wherein a plurality of conducting pads are disposed on an upper surface of the conducting plate; forming a plurality of conducting bumps on a lower surface of the conducting plate; patterning the conducting plate by removing a portion of the conducting plate, wherein the patterned conducting plate has a plurality of conducting sections electrically insulated from each other, and each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; forming an insulating support layer to partially surround the conducting bumps; and disposing a chip on the conducting pads.

Abstract translation: 根据本发明的实施例，提供了一种用于形成芯片封装的方法。 该方法包括：提供导电板，其中多个导电焊盘设置在导电板的上表面上; 在导电板的下表面上形成多个导电凸块; 通过去除导电板的一部分来图案化导电板，其中图案化的导电板具有彼此电绝缘的多个导电部分，并且每个导电凸块电连接到图案化的导电部分的相应一个导电部分 导电板 形成绝缘支撑层以部分地包围所述导电凸块; 并将芯片设置在导电焊盘上。

公开(公告)号：US20150061117A1

公开(公告)日：2015-03-05

申请号：US14015012

申请日：2013-08-30

Applicant: MediaTek Inc.

Inventor： Wen-Sung HSU ,  Ming-Chieh LIN ,  Ta-Jen YU

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L21/4828 ,  H01L21/481 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11912 ,  H01L2224/16238 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8146 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01109 ,  H01L2924/012

Abstract: According to an embodiment of the present invention, a chip package is provided. The chip package includes: a patterned conducting plate having a plurality of conducting sections electrically separated from each other; a plurality of conducting pads disposed on an upper surface of the patterned conducting plate; a chip disposed on the conducting pads; a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; and an insulating support layer partially surrounding the conducting bumps.

Abstract translation: 根据本发明的实施例，提供了一种芯片封装。 芯片封装包括：图案化导电板，其具有彼此电分离的多个导电部分; 设置在所述图案化导电板的上表面上的多个导电焊盘; 设置在导电垫上的芯片; 设置在所述图案化导电板的下表面上的多个导电凸块，其中每个所述导电凸块电连接到所述图案化导电板的相应一个导电部分; 以及部分地围绕导电凸块的绝缘支撑层。