公开(公告)号：US08102236B1

公开(公告)日：2012-01-24

申请号：US12968118

申请日：2010-12-14

Applicant: Robert E. Fontana, Jr. ,  William J. Gallagher ,  Philipp Herget ,  Bucknell C. Webb

Inventor： Robert E. Fontana, Jr. ,  William J. Gallagher ,  Philipp Herget ,  Bucknell C. Webb

IPC: H01F5/00

CPC classification number: H01F17/0006 ,  H01F3/14

Abstract: A thin film inductor according to one embodiment includes one or more arms; one or more conductors passing through each arm; a first ferromagnetic yoke wrapping partially around the one or more conductors in a first of the one or more arms, the first ferromagnetic yoke comprising a magnetic top section, a magnetic bottom section, and via regions positioned on opposites sides of the one or more conductors in the first of the one or more arms, wherein the magnetic top section and magnetic bottom section are coupled together through a low reluctance path in the via regions; and one or more non-magnetic gaps between the top section and the bottom section in at least one of the via regions. Additional systems and methods are also provided.

Abstract translation: 根据一个实施例的薄膜电感器包括一个或多个臂; 穿过每个臂的一个或多个导体; 所述第一铁磁磁轭围绕所述一个或多个臂中的第一个中的所述一个或多个导体包围，所述第一铁磁轭包括磁性顶部，磁性底部部分和位于所述一个或多个导体的相​​对侧上的通孔区域 在一个或多个臂中的第一个中，其中磁性顶部部分和磁性底部部分通过通孔区域中的低磁阻路径耦合在一起; 以及在至少一个通孔区域中的顶部和底部之间的一个或多个非磁性间隙。 还提供了附加的系统和方法。

公开(公告)号：US20080265428A1

公开(公告)日：2008-10-30

申请号：US11740325

申请日：2007-04-26

Applicant: Bucknell C. Webb

Inventor： Bucknell C. Webb

IPC: H01L23/488

CPC classification number: H01L23/49827 ,  H01L23/481 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/13 ,  H01L2224/13012 ,  H01L2224/13025 ,  H01L2924/00014 ,  H05K1/112 ,  H05K3/3436 ,  H05K2201/09854 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A method of modifying via and solder ball shapes for maximizing semiconductor chip or silicon carrier strengths relative to thermal expansion and bending load zero points. The method entails modifying circular annular vias into elliptical annular vias so as to reduce stress concentration factors in the chip or carrier at the vias and solder balls. The reduction in the stress concentration is effected in the semiconductor chip or silicon carrier in regions proximate the vias and in wiring layers at the ends of the vias.

Abstract translation: 一种改变通孔和焊球形状的方法，用于相对于热膨胀和弯曲载荷零点使半导体芯片或硅载体的强度最大化。 该方法需要将圆形环形通孔修改为椭圆形环形通孔，以便减少通孔和焊球处的芯片或载体中的应力集中系数。 应力集中的降低在半导体芯片或硅载体中在通孔附近的区域和通孔末端的布线层中实现。

公开(公告)号：US20080122057A1

公开(公告)日：2008-05-29

申请号：US11932891

申请日：2007-10-31

Applicant: Bucknell C. Webb

Inventor： Bucknell C. Webb

IPC: H01L23/14 ,  H05K3/42

CPC classification number: H01L21/481 ,  H01L23/13 ,  H01L23/147 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/81 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15159 ,  H01L2924/3511 ,  Y10T29/49165 ,  H01L2924/00

Abstract: An apparatus and method providing flexibility to a silicon chip carrier which, in at least one embodiment, comprises multiple chips and a silicon chip carrier having thinned regions between some adjacent chips, thus, allowing for increased flexibility and reduced package warpage.

Abstract translation: 一种为硅芯片载体提供灵活性的装置和方法，该芯片载体在至少一个实施例中包括多个芯片，以及在一些相邻芯片之间具有薄化区域的硅芯片载体，从而允许增加灵活性并减少封装翘曲。

公开(公告)号：US5659436A

公开(公告)日：1997-08-19

申请号：US405261

申请日：1995-03-16

Applicant: Edward John Yarmchuk ,  Mark Delorman Schultz ,  Bucknell C. Webb ,  Timothy Joseph Chainer

Inventor： Edward John Yarmchuk ,  Mark Delorman Schultz ,  Bucknell C. Webb ,  Timothy Joseph Chainer

IPC: G11B5/012 ,  G11B5/55 ,  G11B5/596 ,  G11B21/10

CPC classification number: G11B5/5534 ,  G11B21/10 ,  G11B21/106 ,  G11B5/59633 ,  G11B5/59644

Abstract: A mechanism for servowriting on a storage medium of a storage device. The storage device has a transducer and a servo loop for positioning the transducer with respect to the storage medium. At least one transition is written on a track of the storage medium, while servoing on other transitions previously recorded on the storage medium. A reference waveform is derived as a function of a closed loop response of the servo loop and a position error waveform. The position error waveform corresponds to one or more position errors of the transducer relative to the previously recorded transitions. The reference waveform is usable in writing subsequent tracks on the storage medium. Using the reference waveform for writing subsequent tracks provides a substantial rejection of mechanical disturbances by the servo loop.

Abstract translation: 一种用于在存储设备的存储介质上进行伺服驱动的机制。 存储装置具有用于相对于存储介质定位换能器的换能器和伺服回路。 至少一个转换被写在存储介质的轨道上，同时伺服在先前记录在存储介质上的其它转换。 作为伺服环路的闭环响应和位置误差波形的函数导出参考波形。 位置误差波形对应于传感器相对于先前记录的转换的一个或多个位置误差。 参考波形可用于将后续轨道写入存储介质上。 使用参考波形写入后续轨道可以显着抑制伺服回路的机械扰动。

公开(公告)号：US09758366B2

公开(公告)日：2017-09-12

申请号：US14969329

申请日：2015-12-15

Applicant: Bucknell C. Webb

Inventor： Bucknell C. Webb

IPC: H01L21/00 ,  H01L43/14 ,  H01L43/10 ,  B81C1/00 ,  B81B3/00

CPC classification number: B81B3/0056 ,  B81B2201/012 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/0015 ,  B81C1/00619 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0178 ,  B81C2203/0109 ,  B81C2203/0136 ,  H01H59/0009 ,  H01H2001/0078

Abstract: Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.

公开(公告)号：US09064628B2

公开(公告)日：2015-06-23

申请号：US13477978

申请日：2012-05-22

Applicant: Robert E. Fontana, Jr. ,  Philipp Herget ,  Eugene J. O'Sullivan ,  Lubomyr T. Romankiw ,  Naigang Wang ,  Bucknell C. Webb

Inventor： Robert E. Fontana, Jr. ,  Philipp Herget ,  Eugene J. O'Sullivan ,  Lubomyr T. Romankiw ,  Naigang Wang ,  Bucknell C. Webb

IPC: H01F5/00 ,  H01F27/28 ,  H01F17/00 ,  H01L49/02

CPC classification number: H01F27/2804 ,  H01F5/00 ,  H01F17/0013 ,  H01F2017/0066 ,  H01F2017/0086 ,  H01F2027/2809 ,  H01L28/10

Abstract: A thin film coupled inductor, a thin film spiral inductor, and a system that includes an electronic device and a power supply or power converter incorporating one or more such inductors. A thin film coupled inductor includes a wafer substrate; a bottom yoke comprising a magnetic material above the wafer substrate; a first insulating layer above the bottom yoke; a first conductor above the bottom yoke and separated therefrom by the first insulating layer; a second insulating layer above the first conductor; a second conductor above the second insulating layer; a third insulating layer above the second conductor; and a non-planar top yoke above the third insulating layer, the top yoke comprising a magnetic material.

Abstract translation: 薄膜耦合电感器，薄膜螺旋电感器以及包括电子器件和并入一个或多个此类电感器的电源或功率转换器的系统。 薄膜耦合电感器包括晶片衬底; 底部轭，其包括晶片衬底上方的磁性材料; 在底部轭上方的第一绝缘层; 第一导体，位于底部磁轭之上并由第一绝缘层分离; 在所述第一导体上方的第二绝缘层; 在第二绝缘层上方的第二导体; 在第二导体上方的第三绝缘层; 以及在第三绝缘层上方的非平面顶部磁轭，顶部磁轭包括磁性材料。

公开(公告)号：US09041210B2

公开(公告)日：2015-05-26

申请号：US13527131

申请日：2012-06-19

Applicant: Jeffrey P. Gambino ,  Jessica A. Levy ,  Cameron E. Luce ,  Daniel S. Vanslette ,  Bucknell C. Webb

Inventor： Jeffrey P. Gambino ,  Jessica A. Levy ,  Cameron E. Luce ,  Daniel S. Vanslette ,  Bucknell C. Webb

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through silicon via with sidewall roughness and methods of manufacturing the same are disclosed. The method includes forming a via in a substrate and roughening a sidewall of the via by depositing material within the via. The method further includes removing a backside of the substrate to form a through via with a roughened sidewall structure.

Abstract translation: 公开了一种具有侧壁粗糙度的贯通硅通孔及其制造方法。 该方法包括在基板中形成通孔，并通过在通孔内沉积材料来粗糙化通孔的侧壁。 该方法还包括去除衬底的背面以形成具有粗糙化侧壁结构的通孔。

公开(公告)号：US08759961B2

公开(公告)日：2014-06-24

申请号：US13567567

申请日：2012-08-06

Applicant: Jae-Woong Nah ,  Katsuyuki Sakuma ,  Bucknell C. Webb

Inventor： Jae-Woong Nah ,  Katsuyuki Sakuma ,  Bucknell C. Webb

IPC: H01L23/02

CPC classification number: H01L21/50 ,  H01L21/561 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2224/32145 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/81 ,  H01L2924/014

Abstract: A template having tapered openings can be employed to enable injection of underfill material through gaps having a width less than a lateral dimension of an injector needle for the underfill material. Each tapered opening has a first lateral dimension on an upper side and a second lateral dimension on a lower side. Compliant material portions can be employed to accommodate variations in distance between the template and stacked semiconductor chips and/or an injector head. Optionally, another head can be employed to apply compressed gas to push out the underfill material after the underfill material is applied to the gaps. Multiple injector heads can be employed to simultaneously inject the underfill material at different sites. An adhesive layer can be substituted for the at least one lower compliant material portion.

公开(公告)号：US08754500B2

公开(公告)日：2014-06-17

申请号：US13597412

申请日：2012-08-29

Applicant: Bucknell C. Webb

Inventor： Bucknell C. Webb

IPC: H01L27/08

CPC classification number: H01L23/5227 ,  H01F17/0006 ,  H01F41/046 ,  H01F2017/0066 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor integrated magnetic devices such as inductors, transformers, etc., having laminated magnetic-insulator stack structures are provided, wherein the laminated magnetic-insulator stack structures are formed using electroplating techniques. For example, an integrated laminated magnetic device includes a multilayer stack structure having alternating magnetic and insulating layers formed on a substrate, wherein each magnetic layer in the multilayer stack structure is separated from another magnetic layer in the multilayer stack structure by an insulating layer, and a local shorting structure to electrically connect each magnetic layer in the multilayer stack structure to an underlying magnetic layer in the multilayer stack structure to facilitate electroplating of the magnetic layers using an underlying conductive layer (magnetic or seed layer) in the stack as an electrical cathode/anode for each electroplated magnetic layer in the stack structure.

Abstract translation: 提供具有层压的磁 - 绝缘体堆叠结构的诸如电感器，变压器等的半导体集成磁性器件，其中使用电镀技术形成层叠的磁性 - 绝缘体堆叠结构。 例如，集成层叠磁性装置包括在基板上形成交替的磁性层和绝缘层的多层堆叠结构，其中多层堆叠结构中的每个磁性层通过绝缘层与多层堆叠结构中的另一磁性层分离，以及 局部短路结构，以将多层堆叠结构中的每个磁性层电连接到多层堆叠结构中的下面的磁性层，以便利用叠层中的下面的导电层（磁性或种子层）作为电阴极来促进磁性层的电镀 /阳极，用于堆叠结构中的每个电镀磁性层。

公开(公告)号：US20130106552A1

公开(公告)日：2013-05-02

申请号：US13287942

申请日：2011-11-02

Applicant: Robert E. Fontana, JR. ,  William J. Gallagher ,  Philipp Herget ,  Eugene J. O'Sullivan ,  Naigang Wang ,  Bucknell C. Webb

Inventor： Robert E. Fontana, JR. ,  William J. Gallagher ,  Philipp Herget ,  Eugene J. O'Sullivan ,  Naigang Wang ,  Bucknell C. Webb

IPC: H01F5/00 ,  H01F5/06

CPC classification number: H01F17/0013 ,  H01F2017/0066

Abstract: A thin film inductor according to one embodiment includes a bottom yoke; a first insulating layer above the bottom yoke; one or more conductors above the bottom yoke and separated therefrom by the first insulating layer; a second insulating layer above the one or more conductors; a third insulating layer above the second insulating layer; and a top yoke above the third insulating layer. A thin film inductor according to another embodiment includes a bottom yoke; a first insulating layer above the bottom yoke, the first insulating layer being polymeric; one or more conductors above the bottom yoke and separated therefrom by the first insulating layer; an upper insulating layer above the one or more conductors, the upper insulating layer being polymeric; and a top yoke above the second insulating layer.

Abstract translation: 根据一个实施例的薄膜电感器包括底部轭; 在底部轭上方的第一绝缘层; 一个或多个导体，位于底部磁轭之上并与第一绝缘层分离; 一个或多个导体上方的第二绝缘层; 在所述第二绝缘层上方的第三绝缘层; 以及在第三绝缘层上方的顶部磁轭。 根据另一实施例的薄膜电感器包括底部轭; 在所述底部磁轭上方的第一绝缘层，所述第一绝缘层是聚合物; 一个或多个导体，位于底部磁轭之上并与第一绝缘层分离; 在一个或多个导体上方的上绝缘层，上绝缘层是聚合物; 以及在所述第二绝缘层上方的顶部磁轭。