公开(公告)号：US20140191419A1

公开(公告)日：2014-07-10

申请号：US13995917

申请日：2011-12-22

申请人： Debendra Mallik ,  Ram S. Viswanath ,  Sriram Srinivasan ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Sairam Agraharam

发明人： Debendra Mallik ,  Ram S. Viswanath ,  Sriram Srinivasan ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Sairam Agraharam

IPC分类号： H01L25/065 ,  H01L23/498

CPC分类号： H01L23/49838 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/00

摘要： 3D integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die. In another example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die.

摘要翻译： 描述了具有窗口插入件的3D集成电路封装和形成这种半导体封装的方法。 例如，半导体封装包括衬底。 顶部半导体管芯设置在衬底上方。 具有窗口的插入件设置在基板和顶部半导体管芯之间并与之互连。 底部半导体管芯设置在插入件的窗口中并且互连到顶部半导体管芯。 在另一示例中，半导体封装包括衬底。 顶部半导体管芯设置在衬底上方。 插入器设置在衬底和顶部半导体管芯之间并且互连到衬底和顶部半导体管芯。 底部半导体管芯设置在与插入器相同的平面中并且互连到顶部半导体管芯。

公开(公告)号：US20130178033A1

公开(公告)日：2013-07-11

申请号：US13786372

申请日：2013-03-05

申请人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L29/66

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US06982225B2

公开(公告)日：2006-01-03

申请号：US10660421

申请日：2003-09-10

申请人： Mark T. Bohr

发明人： Mark T. Bohr

IPC分类号： H01L21/31

CPC分类号： H01L23/147 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/157 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49165

摘要： A structure suitable for connecting an integrated circuit to a supporting substrate wherein the structure has thermal expansion characteristics well-matched to the integrated circuit is an interposer. The integrated circuit and the interposer are comprised of bodies that have substantially similar coefficients of thermal expansion. The interposer has a first surface adapted to electrically and mechanically couple to the integrated circuit. The interposer has a second surface adapted to electrically and mechanically couple to a supporting substrate. Electrically conductive vias provide signal pathways between the first surface and the second surface of the interposer. Various circuit elements may be incorporated into the interposer. These circuit elements may be active, passive, or a combination of active and passive elements.

公开(公告)号：US6020244A

公开(公告)日：2000-02-01

申请号：US777552

申请日：1996-12-30

申请人： Scott E. Thompson ,  Paul A. Packan ,  Tahir Ghani ,  Mark Stettler ,  Shahriar S. Ahmed ,  Mark T. Bohr

发明人： Scott E. Thompson ,  Paul A. Packan ,  Tahir Ghani ,  Mark Stettler ,  Shahriar S. Ahmed ,  Mark T. Bohr

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/10

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6659

摘要： An improved well boosting implant which provides better characteristics than traditional halo implants particularly for short channel devices (e.g., 0.25 microns or less). In effect, an implant is distributed across the entire channel with higher concentrations occurring in the center of the channel of the devices having gate lengths less than the critical dimension. This is done by using very large tilt angles (e.g., 30-50.degree.) with a relatively light dopant species and by using a relatively high energy when compared to the traditional halo implants.

摘要翻译： 一种改进的促进良好的植入物，其具有比传统的晕轮植入物更好的特征，特别是对于短通道装置（例如，0.25微米或更小）。 实际上，植入物分布在整个通道上，较高的浓度出现在栅极长度小于临界尺寸的器件的通道的中心。 这通过使用具有相对较轻的掺杂物质的非常大的倾斜角（例如，30-50°）和与传统的晕轮植入物相比使用相当高的能量来完成。

公开(公告)号：US5969404A

公开(公告)日：1999-10-19

申请号：US895325

申请日：1997-07-16

申请人： Mark T. Bohr ,  Mohsen Alavi

发明人： Mark T. Bohr ,  Mohsen Alavi

IPC分类号： H01L21/82 ,  H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002

摘要： A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections. The fusible link device of the invention includes a silicide layer and a polysilicon layer formed on the silicide layer and has a first unprogrammed resistance. The silicide layer agglomerates to form an electrical discontinuity in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased to a second programmed resistance

摘要翻译： 一种设置在半导体衬底上用于提供任意电连接的可熔连接装置。 本发明的熔断连接装置包括在硅化物层上形成的硅化物层和多晶硅层，并具有第一未编程电阻。 硅化物层聚集形成响应于跨越硅化物层施加的预定编程电位的电中断，使得可熔接头装置的电阻可以选择性地增加到第二编程电阻

公开(公告)号：US5708291A

公开(公告)日：1998-01-13

申请号：US537283

申请日：1995-09-29

申请人： Mark T. Bohr ,  Mohsen Alavi

发明人： Mark T. Bohr ,  Mohsen Alavi

IPC分类号： H01L21/82 ,  H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002

摘要： A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections. The fusible link device of the invention includes a silicide layer and a polysilicon layer formed on the silicide layer and has a first un-programmed resistance. The silicide layer agglomerates to form an electrical discontinuity in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased to a second programmed resistance.

摘要翻译： 一种设置在半导体衬底上用于提供任意电连接的可熔连接装置。 本发明的可熔连接装置包括硅化物层和形成在硅化物层上并具有第一非编程电阻的多晶硅层。 硅化物层聚集形成响应于跨过硅化物层施加的预定编程电位的电中断，使得熔丝连接装置的电阻可以选择性地增加到第二编程电阻。

公开(公告)号：US5091332A

公开(公告)日：1992-02-25

申请号：US615445

申请日：1990-11-19

申请人： Mark T. Bohr ,  Lawrence N. Brigham, Jr. ,  Shahab Hossaini

发明人： Mark T. Bohr ,  Lawrence N. Brigham, Jr. ,  Shahab Hossaini

IPC分类号： H01L21/761 ,  H01L21/266 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

CPC分类号： H01L21/76218 ,  H01L21/266 ,  H01L21/76202 ,  H01L21/823892 ,  H01L27/0928

摘要： Front end processing for a CMOS substrate resulting in the formation of n-wells, p-wells, channel stops and field oxide regions. Both the n-type and p-type dopant are implanted through silicon nitride members with one type dopant being first blocked by a first layer of photoresist and the second dopant by a second layer of photoresist. The field oxide regions are grown after the first dopant is implanted. Relatively low level ion implantation is used and additional threshold adjusting implants are not needed.

摘要翻译： 导致CMOS衬底的前端处理导致形成n阱，p阱，通道停止和场氧化物区域。 n型和p型掺杂剂都通过氮化硅构件注入，其中一种类型的掺杂剂首先被第一光致抗蚀剂层阻挡，而第二掺杂剂被第二层光致抗蚀剂阻挡。 在植入第一掺杂剂之后，生长场氧化物区域。 使用相对较低水平的离子注入，并且不需要额外的阈值调整植入物。

公开(公告)号：US4372034A

公开(公告)日：1983-02-08

申请号：US248013

申请日：1981-03-26

申请人： Mark T. Bohr

发明人： Mark T. Bohr

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/265 ,  H01L21/31

CPC分类号： H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76804

摘要： A process is described for forming an opening for a contact member through a deposited oxide layer and thermally grown oxide layer. Where the deposited oxide layer is rich in phosphorus, a wet etchant is used to etch through the deposited oxide layer. This results in a tapered opening through the deposited oxide layer. Then a plasma etchant is used to form an opening through the thermally grown oxide in alignment with an opening through a photoresist layer.

摘要翻译： 描述了通过沉积的氧化物层和热生长的氧化物层形成用于接触构件的开口的方法。 当沉积的氧化物层富含磷时，使用湿蚀刻剂来蚀刻沉积的氧化物层。 这导致通过沉积的氧化物层的锥形开口。 然后使用等离子体蚀刻剂形成通过热生长氧化物的开口，其与通过光致抗蚀剂层的开口对准。

公开(公告)号：US4282648A

公开(公告)日：1981-08-11

申请号：US133580

申请日：1980-03-24

申请人： Kenneth K. Yu ,  Mark T. Bohr ,  Mark B. Seidenfeld

发明人： Kenneth K. Yu ,  Mark T. Bohr ,  Mark B. Seidenfeld

IPC分类号： H01L27/08 ,  H01L21/225 ,  H01L21/336 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L21/22

CPC分类号： H01L21/823878 ,  H01L21/2253 ,  H01L21/743 ,  H01L21/76218 ,  H01L29/0638 ,  Y10S148/053 ,  Y10S148/07 ,  Y10S148/117

摘要： A CMOS Process for fabricating channel stops which are substantially formed as a by-product of growing a field oxide is described. A p-type region is formed at an edge (or edges) of an n-type well through an opening in a silicon nitride layer. An oxide is grown at the opening. As the oxide grows, n-type dopant from the n-type well accumulates at the edge of the oxide, forming a more highly doped n-type region. Simultaneously, an adjacent p-type region is formed under the oxide from the p-type dopant. The process also permits easy fabrication of a buried contact to the p-channel device thus eliminating the need for a metal contact when forming a bistable circuit.

摘要翻译： 描述了用于制造基本上形成为生长场氧化物的副产品的通道停止件的CMOS工艺。 p型区域形成在n型阱的边缘（或边缘）中，穿过氮化硅层中的开口。 在开口处生长氧化物。 随着氧化物生长，来自n型阱的n型掺杂剂在氧化物的边缘积聚，形成更高掺杂的n型区域。 同时，在p型掺杂剂的氧化物之下形成相邻的p型区域。 该工艺还允许容易地制造到p沟道器件的掩埋接触，从而在形成双稳态电路时不需要金属接触。

公开(公告)号：US11037923B2

公开(公告)日：2021-06-15

申请号：US13538935

申请日：2012-06-29

申请人： Mark T. Bohr ,  Stephen M. Cea ,  Barbara A. Chappell

发明人： Mark T. Bohr ,  Stephen M. Cea ,  Barbara A. Chappell

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L21/84

摘要： Through gate fin isolation for non-planar transistors in a microelectronic device, such as an integrated circuit (IC). In embodiments, ends of adjacent semiconductor fins are electrically isolated from each other with an isolation region that is self-aligned to gate electrodes of the semiconductor fins enabling higher transistor packing density and other benefits. In an embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes of a fixed pitch, a first subset of placeholder stripes is removed and isolation cuts made into the semiconductor fins in openings resulting from the first subset removal while a second subset of the placeholder stripes is replaced with gate electrodes.