公开(公告)号：US4282648A

公开(公告)日：1981-08-11

申请号：US133580

申请日：1980-03-24

申请人： Kenneth K. Yu ,  Mark T. Bohr ,  Mark B. Seidenfeld

发明人： Kenneth K. Yu ,  Mark T. Bohr ,  Mark B. Seidenfeld

IPC分类号： H01L27/08 ,  H01L21/225 ,  H01L21/336 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L21/22

CPC分类号： H01L21/823878 ,  H01L21/2253 ,  H01L21/743 ,  H01L21/76218 ,  H01L29/0638 ,  Y10S148/053 ,  Y10S148/07 ,  Y10S148/117

摘要： A CMOS Process for fabricating channel stops which are substantially formed as a by-product of growing a field oxide is described. A p-type region is formed at an edge (or edges) of an n-type well through an opening in a silicon nitride layer. An oxide is grown at the opening. As the oxide grows, n-type dopant from the n-type well accumulates at the edge of the oxide, forming a more highly doped n-type region. Simultaneously, an adjacent p-type region is formed under the oxide from the p-type dopant. The process also permits easy fabrication of a buried contact to the p-channel device thus eliminating the need for a metal contact when forming a bistable circuit.

摘要翻译： 描述了用于制造基本上形成为生长场氧化物的副产品的通道停止件的CMOS工艺。 p型区域形成在n型阱的边缘（或边缘）中，穿过氮化硅层中的开口。 在开口处生长氧化物。 随着氧化物生长，来自n型阱的n型掺杂剂在氧化物的边缘积聚，形成更高掺杂的n型区域。 同时，在p型掺杂剂的氧化物之下形成相邻的p型区域。 该工艺还允许容易地制造到p沟道器件的掩埋接触，从而在形成双稳态电路时不需要金属接触。

公开(公告)号：US4409259A

公开(公告)日：1983-10-11

申请号：US403116

申请日：1982-07-29

申请人： Mark T. Bohr ,  Kenneth K. Yu ,  Ronald J. C. Chwang ,  C. Neil Berglund

发明人： Mark T. Bohr ,  Kenneth K. Yu ,  Ronald J. C. Chwang ,  C. Neil Berglund

IPC分类号： G11C5/00 ,  G11C11/404 ,  H01L23/556 ,  H01L27/108 ,  H01L29/78 ,  B05D5/12 ,  H01L27/02

CPC分类号： H01L27/10805 ,  G11C11/404 ,  G11C5/005 ,  H01L23/556 ,  H01L2924/0002

摘要： A high density CMOS dynamic RAM cell comprising a transistor and capacitance means formed in an n-well is disclosed. The capacitance means includes a polysilicon plate member disposed above a p-type region formed in the n-well. A buried contact, extending from the plate member, pierces the p-type region and contacts the well. In addition to the capacitance associated with the plate member, p-type region and well, capacitance is obtained between the side walls of the n-type regions and p-type regions.

摘要翻译： 公开了一种包括形成在n阱中的晶体管和电容装置的高密度CMOS动态RAM单元。 电容装置包括设置在形成在n阱中的p型区域上方的多晶硅板构件。 从板构件延伸的埋入触头刺穿p型区域并与阱接触。 除了与板构件，p型区域和阱相关联的电容之外，在n型区域和p型区域的侧壁之间获得电容。

公开(公告)号：US4364075A

公开(公告)日：1982-12-14

申请号：US182870

申请日：1980-09-02

申请人： Mark T. Bohr ,  Kenneth K. Yu ,  Ronald J. C. Chwang ,  Neil C. Berglund

发明人： Mark T. Bohr ,  Kenneth K. Yu ,  Ronald J. C. Chwang ,  Neil C. Berglund

IPC分类号： G11C11/401 ,  G11C5/00 ,  G11C11/404 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/556 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L27/02

CPC分类号： H01L27/10805 ,  G11C11/404 ,  G11C5/005 ,  H01L23/556 ,  H01L2924/0002

摘要： A high density CMOS dynamic RAM cell comprising a transistor and capacitance means formed in an n-well is disclosed. The capacitance means includes a polysilicon plate member disposed above a p-type region formed in the n-well. A buried contact, extending from the plate member, pierces the p-type region and contacts the well. In addition to the capacitance associated with the plate member, p-type region and well, capacitance is obtained between the side walls of the n-type regions and p-type regions.

摘要翻译： 公开了一种包括形成在n阱中的晶体管和电容装置的高密度CMOS动态RAM单元。 电容装置包括设置在形成在n阱中的p型区域上方的多晶硅板构件。 从板构件延伸的埋入触头刺穿p型区域并与阱接触。 除了与板构件，p型区域和阱相关联的电容之外，在n型区域和p型区域的侧壁之间获得电容。

公开(公告)号：US20160133749A1

公开(公告)日：2016-05-12

申请号：US15001042

申请日：2016-01-19

申请人： Mark T. Bohr

发明人： Mark T. Bohr

IPC分类号： H01L29/78 ,  H01L29/167 ,  H01L29/161 ,  H01L29/165 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/7848 ,  H01L21/845 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7378 ,  H01L29/7834 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder.

公开(公告)号：US09129958B2

公开(公告)日：2015-09-08

申请号：US13995917

申请日：2011-12-22

申请人： Debendra Mallik ,  Ram S. Viswanath ,  Sriram Srinivasan ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Sairam Agraharam

发明人： Debendra Mallik ,  Ram S. Viswanath ,  Sriram Srinivasan ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Sairam Agraharam

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L23/13 ,  H01L25/065

CPC分类号： H01L23/49838 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/00

摘要： 3D integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die. In another example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die.

摘要翻译： 描述了具有窗口插入件的3D集成电路封装和形成这种半导体封装的方法。 例如，半导体封装包括衬底。 顶部半导体管芯设置在衬底上方。 具有窗口的插入件设置在基板和顶部半导体管芯之间并与之互连。 底部半导体管芯设置在插入件的窗口中并且互连到顶部半导体管芯。 在另一示例中，半导体封装包括衬底。 顶部半导体管芯设置在衬底上方。 插入器设置在衬底和顶部半导体管芯之间并且互连到衬底和顶部半导体管芯。 底部半导体管芯设置在与插入器相同的平面中并且互连到顶部半导体管芯。

公开(公告)号：US08741720B2

公开(公告)日：2014-06-03

申请号：US13857578

申请日：2013-04-05

申请人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

发明人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

IPC分类号： H01L21/336

CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

摘要： A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

摘要翻译： 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

公开(公告)号：US20130240950A1

公开(公告)日：2013-09-19

申请号：US13886939

申请日：2013-05-03

申请人： Mark T. Bohr

发明人： Mark T. Bohr

IPC分类号： H01L29/78

CPC分类号： H01L29/7848 ,  H01L21/845 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7378 ,  H01L29/7834 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder.

摘要翻译： 描述了具有无衬底外延源极/漏极区域的半导体器件及其形成方法。 在一个实施例中，半导体器件包括在衬底上的栅极堆叠。 栅极堆叠由栅极电介质层上方的栅电极构成，并且位于衬底中的沟道区之上。 半导体器件还包括在沟道区两侧的衬底中的一对源/漏区。 该源极/漏极区域与栅极介质层直接接触，并且该源极/漏极区域的晶格常数不同于沟道区域的晶格常数。 在一个实施例中，半导体器件通过使用电介质栅叠层占位符形成。

公开(公告)号：US20110156107A1

公开(公告)日：2011-06-30

申请号：US12655408

申请日：2009-12-30

申请人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

摘要翻译： 晶体管包括衬底，衬底上的一对间隔物，衬底上的栅介质层和一对间隔物之间​​，栅极电介质层上的栅电极层和一对衬垫之间的绝缘帽层 栅极电极层和一对间隔物之间​​，以及与该对间隔物相邻的一对扩散区域。 绝缘盖层形成了与栅极自对准的防蚀结构，并防止接触蚀刻暴露栅电极，从而防止栅极和接触之间的短路。 绝缘体盖层能够进行自对准触点，允许对图案化限制更坚固的较宽触点的初始图案化。

公开(公告)号：US07821044B2

公开(公告)日：2010-10-26

申请号：US12009122

申请日：2008-01-15

申请人： Mark T. Bohr ,  Steven J. Keating ,  Thomas A. Letson ,  Anand S. Murthy ,  Donald W. O'Neill ,  Willy Rachmady

发明人： Mark T. Bohr ,  Steven J. Keating ,  Thomas A. Letson ,  Anand S. Murthy ,  Donald W. O'Neill ,  Willy Rachmady

IPC分类号： H01L21/336 ,  H01L29/06

CPC分类号： H01L29/045 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.

摘要翻译： 实施例是改进的晶体管结构和制造该结构的方法。 特别地，实施例的湿蚀刻形成具有改进的尖端形状的源极和漏极区域，以通过改善短沟道效应的控制，增加饱和电流，改善冶金栅极长度的控制，增加载流子迁移率来提高晶体管的性能 并且在源极和漏极与硅化物之间的界面处降低接触电阻。

公开(公告)号：US07180195B2

公开(公告)日：2007-02-20

申请号：US10739726

申请日：2003-12-17

申请人： Mark T. Bohr ,  Robert W. Martell

发明人： Mark T. Bohr ,  Robert W. Martell

IPC分类号： H01L23/48 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L24/02 ,  H01L23/5226 ,  H01L23/5286 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00

摘要： An apparatus comprising: a die having a top metal layer, the top metal layer comprised of at least a first metal line and a second metal line; a passivation layer covering the top metal layer; a C4 bump on the passivation layer; and a first passivation opening and a second passivation opening in the passivation layer, the first passivation opening to connect the first metal line to the C4 bump, and the second passivation opening to connect the second metal line to the C4 bump.