公开(公告)号：US10002840B1

公开(公告)日：2018-06-19

申请号：US15672006

申请日：2017-08-08

Applicant: Micron Technology, Inc.

Inventor： Mayukhee Das ,  Jonathan S. Hacker ,  Christopher J. Gambee ,  Chandra S. Tiwari

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L22/32 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/03011 ,  H01L2224/0345 ,  H01L2224/03921 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13026 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/01074

Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad, and a conductive interconnect can extend from the conductive structure.

公开(公告)号：US09966347B2

公开(公告)日：2018-05-08

申请号：US15624493

申请日：2017-06-15

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Jaspreet S. Gandhi ,  Christopher J. Gambee ,  Satish Yeldandi

IPC: H01L21/20 ,  H01L21/768 ,  H01L29/43 ,  H01L29/84 ,  H01L23/498 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/038 ,  H01L2224/0382 ,  H01L2224/039 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05583 ,  H01L2224/05584 ,  H01L2224/05687 ,  H01L2224/94 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/365 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/053 ,  H01L2924/054 ,  H01L2224/03

Abstract: The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.

公开(公告)号：US09704781B2

公开(公告)日：2017-07-11

申请号：US14084037

申请日：2013-11-19

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Jaspreet S. Gandhi ,  Christopher J. Gambee ,  Satish Yeldandi

IPC: H01L23/498 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/48 ,  H01L21/44 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/038 ,  H01L2224/0382 ,  H01L2224/039 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05583 ,  H01L2224/05584 ,  H01L2224/05687 ,  H01L2224/94 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/365 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/053 ,  H01L2924/054 ,  H01L2224/03

Abstract: The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.

公开(公告)号：US09129869B2

公开(公告)日：2015-09-08

申请号：US14186869

申请日：2014-02-21

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Luke G. England ,  Christopher J. Gambee

IPC: H01L21/4763 ,  H01L23/00 ,  H01L21/027 ,  H01L21/311 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L24/14 ,  H01L21/0274 ,  H01L21/311 ,  H01L21/56 ,  H01L23/291 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/35121 ,  H01L2924/365 ,  H01L2924/3651 ,  H01L2924/381 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/206 ,  H01L2224/05552 ,  H01L2224/11

Abstract: Methods of fabricating interconnect structures for semiconductor dice comprise forming conductive elements in contact with bond pads on an active surface over a full pillar diameter of the conductive elements, followed by application of a photodefinable material comprising a photoresist to the active surface and over the conductive elements. The polyimide material is selectively exposed and developed to remove photodefinable material covering at least tops of the conductive elements. Semiconductor dice and semiconductor die assemblies are also disclosed.

Abstract translation: 制造用于半导体晶片的互连结构的方法包括形成与导电元件的全柱直径上的有源表面上的接合焊盘接触的导电元件，随后将包含光致抗蚀剂的可光限定材料施加到有源表面上并在导电元件上 。 聚酰亚胺材料被选择性地曝光和显影以除去覆盖至少导电元件顶部的可光限定材料。 还公开了半导体管芯和半导体管芯组件。

公开(公告)号：US20150137353A1

公开(公告)日：2015-05-21

申请号：US14084037

申请日：2013-11-19

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Jaspreet S. Gandhi ,  Christopher J. Gambee ,  Satish Yeldandi

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/038 ,  H01L2224/0382 ,  H01L2224/039 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05583 ,  H01L2224/05584 ,  H01L2224/05687 ,  H01L2224/94 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/365 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/053 ,  H01L2924/054 ,  H01L2224/03

Abstract: The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.

Abstract translation: 本技术涉及制造具有用于管芯到管芯和/或封装到封装互连或其它类型互连的具有凸块下金属（UBM）结构的半导体管芯。 在一个实施例中，用于在半导体管芯上形成凸块状凸起的金属（UBM）结构的方法包括通过将第一材料镀在种子结构的第一区域上并在第一材料上沉积第二材料来构造UBM柱。 第一材料具有第一电位，第二材料具有大于第一电位的第二电势。 该方法还包括减小第一材料和第二材料之间的电位差，然后去除UBM柱之间的种子结构的第二区域，从而在半导体管芯上形成UBM结构。

公开(公告)号：US09034769B2

公开(公告)日：2015-05-19

申请号：US13712699

申请日：2012-12-12

Applicant: Micron Technology, Inc.

Inventor： Mark A. Bossler ,  Jaspreet S. Gandhi ,  Christopher J. Gambee ,  Randall S. Parker

IPC: H01L21/302 ,  H01L21/461 ,  H01L23/538 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L23/53238 ,  H01L21/02068 ,  H01L21/02238 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for selective removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The method comprises oxidizing a semiconductor structure comprising a substrate and at least one copper feature and removing a portion of the substrate using an etchant comprising SF6 without forming copper sulfide on the at least one copper feature. Additional methods are also disclosed, as well as semiconductor structures produced from such methods.

Abstract translation: 一种用于从衬底选择性地去除材料的方法，而不损害填充通孔的铜，并且至少部分地延伸通过衬底。 该方法包括氧化包括基底和至少一个铜特征的半导体结构，并且使用包含SF 6的蚀刻剂去除一部分基底，而不在至少一个铜特征上形成硫化铜。 还公开了另外的方法，以及由这些方法制备的半导体结构。