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公开(公告)号:US20190341325A1
公开(公告)日:2019-11-07
申请号:US16431988
申请日:2019-06-05
Applicant: Micron Technology, Inc.
Inventor: James M. Derderian , Andrew M. Bayless , Xiao Li
IPC: H01L23/367 , H01L23/532 , H01L23/498
Abstract: A semiconductor device assembly having a semiconductor device attached to a substrate with a foil layer on a surface of the substrate. A layer of adhesive connects the substrate to a first surface of the semiconductor device. The semiconductor device assembly enables processing on the second surface of the semiconductor device. An energy pulse may be applied to the foil layer causing an exothermic reaction to the foil layer that releases the substrate from the semiconductor device. The semiconductor device assembly may include a release layer positioned between the foil layer and the layer of adhesive that connects the substrate to the semiconductor device. The heat generated by the exothermic reaction breaks down the release layer to release the substrate from the semiconductor device. The energy pulse may be an electric charge, a heat pulse, or may be applied from a laser.
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公开(公告)号:US10431519B1
公开(公告)日:2019-10-01
申请号:US15969978
申请日:2018-05-03
Applicant: Micron Technology, Inc.
Inventor: James M. Derderian , Andrew M. Bayless , Xiao Li
IPC: H01L23/00 , H01L23/367 , H01L23/532 , H01L23/498 , B32B43/00 , B32B7/12
Abstract: A semiconductor device assembly having a semiconductor device attached to a substrate with a foil layer on a surface of the substrate. A layer of adhesive connects the substrate to a first surface of the semiconductor device. The semiconductor device assembly enables processing on the second surface of the semiconductor device. An energy pulse may be applied to the foil layer causing an exothermic reaction to the foil layer that releases the substrate from the semiconductor device. The semiconductor device assembly may include a release layer positioned between the foil layer and the layer of adhesive that connects the substrate to the semiconductor device. The heat generated by the exothermic reaction breaks down the release layer to release the substrate from the semiconductor device. The energy pulse may be an electric charge, a heat pulse, or may be applied from a laser.
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公开(公告)号:US20190252337A1
公开(公告)日:2019-08-15
申请号:US15898019
申请日:2018-02-15
Applicant: Micron Technology, Inc.
Inventor: James M. Derderian
IPC: H01L23/00 , H01L21/268 , H01L21/683 , H01L21/78 , H01L21/67 , B23K1/005
CPC classification number: H01L24/11 , B23K1/0056 , B23K2101/40 , H01L21/268 , H01L21/67115 , H01L21/67248 , H01L21/6836 , H01L21/78 , H01L24/94 , H01L2221/68327 , H01L2224/117 , H01L2224/11849
Abstract: Methods of reflowing electrically conductive elements on a wafer may involve directing a laser beam toward a region of a surface of a wafer supported on a film of a film frame to reflow at least one electrically conductive element on the surface of the wafer. In some embodiments, the wafer may be detached from a carrier substrate and be secured to the film frame before laser reflow. Apparatus for performing the methods, and methods of repairing previously reflowed conductive elements on a wafer are also disclosed.
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34.
公开(公告)号:US10163755B2
公开(公告)日:2018-12-25
申请号:US15498321
申请日:2017-04-26
Applicant: Micron Technology, Inc.
Inventor: Sameer S. Vadhavkar , Xiao Li , Steven K. Groothuis , Jian Li , Jaspreet S. Gandhi , James M. Derderian , David R. Hembree
IPC: H01L21/52 , H01L21/54 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/44 , H01L25/00 , H01L25/18 , H01L23/053 , H01L23/367 , H01L23/373
Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.
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35.
公开(公告)号:US10126357B2
公开(公告)日:2018-11-13
申请号:US15660387
申请日:2017-07-26
Applicant: Micron Technology, Inc.
Inventor: Jaspreet S. Gandhi , Michel Koopmans , James M. Derderian
Abstract: Apparatus for testing semiconductor devices comprising die stacks, the apparatus comprising a substrate having an array of pockets in a surface thereof arranged to correspond to conductive elements protruding from a semiconductor device to be tested. The pockets include conductive contacts with traces extending to conductive pads, which may be configured as test pads, jumper pads, edge connects or contact pads. The substrate may comprise a semiconductor wafer or wafer segment and, if the latter, multiple segments may be received in recesses in a fixture. Testing may be effected using a probe card, a bond head carrying conductive pins, or through conductors carried by the fixture.
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36.
公开(公告)号:US20170229439A1
公开(公告)日:2017-08-10
申请号:US15498321
申请日:2017-04-26
Applicant: Micron Technology, Inc.
Inventor: Sameer S. Vadhavkar , Xiao Li , Steven K. Groothuis , Jian Li , Jaspreet S. Gandhi , James M. Derderian , David R. Hembree
IPC: H01L25/00 , H01L21/56 , H01L23/373 , H01L23/00 , H01L23/44 , H01L25/18 , H01L23/367
CPC classification number: H01L23/44 , H01L21/50 , H01L21/52 , H01L21/54 , H01L21/563 , H01L23/04 , H01L23/053 , H01L23/3128 , H01L23/3675 , H01L23/3736 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/73 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/1134 , H01L2224/13025 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/1329 , H01L2224/133 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/1703 , H01L2224/17181 , H01L2224/17519 , H01L2224/2919 , H01L2224/29191 , H01L2224/2929 , H01L2224/2939 , H01L2224/29393 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/83101 , H01L2224/83102 , H01L2224/83104 , H01L2224/83424 , H01L2224/83447 , H01L2224/8388 , H01L2224/92125 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06589 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/156 , H01L2924/16235 , H01L2924/16251 , H01L2924/1815 , H01L2924/0715 , H01L2924/00014 , H01L2924/01006 , H01L2924/014 , H01L2924/01047 , H01L2924/00012 , H01L2924/0665 , H01L2924/00
Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.
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37.
公开(公告)号:US20160343689A1
公开(公告)日:2016-11-24
申请号:US15229618
申请日:2016-08-05
Applicant: Micron Technology, Inc.
Inventor: Jaspreet S. Gandhi , Wayne H. Huang , James M. Derderian
IPC: H01L25/065 , H01L23/00 , H01L25/00
CPC classification number: H01L25/0657 , H01L23/00 , H01L23/34 , H01L23/3675 , H01L23/4012 , H01L23/42 , H01L23/49811 , H01L23/49827 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/81 , H01L25/043 , H01L25/065 , H01L25/0756 , H01L25/50 , H01L2224/05599 , H01L2224/11 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/16225 , H01L2224/16503 , H01L2224/73253 , H01L2224/81815 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06586 , H01L2225/06589 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01327 , H01L2924/05032 , H01L2924/15311 , H01L2924/181 , H01L2924/00012
Abstract: Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member.
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公开(公告)号:US20240284590A1
公开(公告)日:2024-08-22
申请号:US18436892
申请日:2024-02-08
Applicant: Micron Technology, Inc.
Inventor: Chan H. Yoo , James M. Derderian , Walter L. Moden , Christopher Glancey
IPC: H05K1/02 , G01R31/309 , H05K3/28
CPC classification number: H05K1/0269 , G01R31/309 , H05K3/28
Abstract: Aspects of the present disclosure configure a processor to detect faults in a printed circuit board (PCB) solder mask using an optical waveguide. The processor directs an optical beam to an input of one or more optical waveguides embedded in a protective coating layer of a PCB, the protective coating layer being adjacent to one or more traces of the PCB. The processor measures a beam characteristic of the optical beam that is output by the one or more optical waveguides. The processor detects a disruption of the optical beam that is output by the one or more optical waveguides based on the beam characteristic. The processor detects a fault in the protective coating layer of the PCB based on detecting the disruption of the optical beam that is output by the one or more optical waveguides.
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39.
公开(公告)号:US11776877B2
公开(公告)日:2023-10-03
申请号:US17335994
申请日:2021-06-01
Applicant: Micron Technology, Inc.
Inventor: Sameer S. Vadhavkar , Xiao Li , Steven K. Groothuis , Jian Li , Jaspreet S. Gandhi , James M. Derderian , David R. Hembree
IPC: H01L23/44 , H01L25/00 , H01L21/56 , H01L23/00 , H01L23/367 , H01L25/18 , H01L23/04 , H01L21/50 , H01L25/065 , H01L23/373 , H01L21/52 , H01L21/54 , H01L23/053 , H01L23/31
CPC classification number: H01L23/44 , H01L21/50 , H01L21/52 , H01L21/54 , H01L21/563 , H01L23/04 , H01L23/053 , H01L23/3128 , H01L23/3675 , H01L23/3736 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L24/29 , H01L24/33 , H01L2224/1134 , H01L2224/131 , H01L2224/133 , H01L2224/13025 , H01L2224/1329 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/1703 , H01L2224/17181 , H01L2224/17519 , H01L2224/2919 , H01L2224/2929 , H01L2224/2939 , H01L2224/29191 , H01L2224/29393 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/8388 , H01L2224/83101 , H01L2224/83102 , H01L2224/83104 , H01L2224/83424 , H01L2224/83447 , H01L2224/92125 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06589 , H01L2924/1431 , H01L2924/1434 , H01L2924/156 , H01L2924/15311 , H01L2924/16235 , H01L2924/16251 , H01L2924/1815 , H01L2224/29191 , H01L2924/0715 , H01L2224/2929 , H01L2924/00014 , H01L2224/29393 , H01L2924/01006 , H01L2224/2939 , H01L2924/014 , H01L2224/83447 , H01L2924/00014 , H01L2224/83424 , H01L2924/00014 , H01L2224/1134 , H01L2924/00014 , H01L2224/13147 , H01L2924/00014 , H01L2224/13155 , H01L2924/00014 , H01L2224/131 , H01L2924/014 , H01L2224/13111 , H01L2924/01047 , H01L2224/1329 , H01L2924/00014 , H01L2224/133 , H01L2924/00014 , H01L2224/16145 , H01L2924/00012 , H01L2224/83104 , H01L2924/00014 , H01L2224/83102 , H01L2924/00014 , H01L2224/2919 , H01L2924/0665 , H01L2224/83101 , H01L2924/00014 , H01L2224/73204 , H01L2224/16145 , H01L2224/32145 , H01L2924/00
Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.
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公开(公告)号:US11081458B2
公开(公告)日:2021-08-03
申请号:US15898019
申请日:2018-02-15
Applicant: Micron Technology, Inc.
Inventor: James M. Derderian
IPC: H01L23/00 , H01L21/683 , H01L21/268 , H01L21/78 , H01L21/67 , B23K1/005 , B23K101/40
Abstract: Methods of reflowing electrically conductive elements on a wafer may involve directing a laser beam toward a region of a surface of a wafer supported on a film of a film frame to reflow at least one electrically conductive element on the surface of the wafer. In some embodiments, the wafer may be detached from a carrier substrate and be secured to the film frame before laser reflow. Apparatus for performing the methods, and methods of repairing previously reflowed conductive elements on a wafer are also disclosed.
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