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    Active thermal control for stacked IC devices
    31.
    发明授权
    Active thermal control for stacked IC devices 有权
    堆叠式IC器件的主动热控制

    公开(公告)号：US08987062B2

    公开(公告)日：2015-03-24

    申请号：US14056212

    申请日：2013-10-17

    Applicant: QUALCOMM Incorporated

    Inventor： Shiqun Gu ,  Matthew Michael Nowak ,  Thomas Robert Toms

    IPC: H01L23/24 ,  H05K7/20 ,  H01L23/38 ,  H01L25/065

    CPC classification number: H05K7/20 ,  H01L23/38 ,  H01L25/0657 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2224/05599

    Abstract: Thermal conductivity in a stacked IC device can be improved by constructing one or more active temperature control devices within the stacked IC device. In one embodiment, the control devices are thermal electric (TE) devices, such as Peltier devices. The TE devices can then be selectively controlled to remove or add heat, as necessary, to maintain the stacked IC device within a defined temperature range. The active temperature control elements can be P-N junctions created in the stacked IC device and can serve to move the heat laterally and/or vertically, as desired.

    Abstract translation: 可以通过在堆叠的IC器件内构造一个或多个有源温度控制器件来提高层叠IC器件中的导热性。 在一个实施例中，控制装置是诸如珀耳帖装置之类的热电（TE）装置。 然后可根据需要选择性地控制TE器件去除或加热，以将堆叠的IC器件保持在规定的温度范围内。 活性温度控制元件可以是在堆叠的IC器件中产生的P-N结，并且可以根据需要用于横向和/或垂直地移动热量。

    Semiconductor device and methods of making semiconductor device using graphene
    34.
    发明授权
    Semiconductor device and methods of making semiconductor device using graphene 有权
    使用石墨烯制造半导体器件的半导体器件和方法

    公开(公告)号：US08796741B2

    公开(公告)日：2014-08-05

    申请号：US13644720

    申请日：2012-10-04

    Applicant: Qualcomm Incorporated

    Inventor： Shiqun Gu ,  Yang Du

    IPC: H01L27/10

    CPC classification number: H01L27/0688 ,  H01L21/2007 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/1606

    Abstract: A semiconductor device and methods of making a semiconductor device using graphene are described. A monolithic three dimensional integrated circuit device includes a first layer having first active devices. The monolithic three dimensional integrated circuit device also includes a second layer having second active devices that each include a graphene portion. The second layer can be fabricated on the first layer to form a stack of active devices. A base substrate may support the stack of active devices.

    Abstract translation: 描述半导体器件以及使用石墨烯制造半导体器件的方法。 单片三维集成电路器件包括具有第一有源器件的第一层。 单片三维集成电路器件还包括具有第二有源器件的第二层，每个有源器件均包括石墨烯部分。 可以在第一层上制造第二层以形成有源器件的堆叠。 基底可以支撑有源器件的堆叠。

    STT MRAM MAGNETIC TUNNEL JUNCTION ARCHITECTURE AND INTEGRATION
    35.
    发明申请
    STT MRAM MAGNETIC TUNNEL JUNCTION ARCHITECTURE AND INTEGRATION 审中-公开
    STT MRAM磁铁隧道结构和集成

    公开(公告)号：US20140015080A1

    公开(公告)日：2014-01-16

    申请号：US14036409

    申请日：2013-09-25

    Applicant: QUALCOMM Incorporated

    Inventor： Seung H. Kang ,  Xia Li ,  Shiqun Gu ,  Kangho Lee ,  Xiaochun Zhu

    IPC: H01L43/02 ,  H01L43/12

    CPC classification number: H01L27/222 ,  H01L43/08 ,  H01L43/12

    Abstract: A magnetic tunnel junction (MTJ) device for a magnetic random access memory (MRAM) includes a first conductive interconnect communicating with at least one control device and a first electrode coupling to the first conductive interconnect through a via opening formed in a dielectric passivation barrier using a first mask. The device has an MTJ stack for storing data, coupled to the first electrode. A portion of the MTJ stack has lateral dimensions based upon a second mask. The portion defined by the second mask is over the contact via. A second electrode is coupled to the MTJ stack and also has a lateral dimension defined by the second mask. The first electrode and a portion of the MTJ stack are defined by a third mask. A second conductive interconnect is coupled to the second electrode and at least one other control device.

    Abstract translation: 用于磁性随机存取存储器（MRAM）的磁性隧道结（MTJ）装置包括与至少一个控制装置通信的第一导电互连和通过形成在电介质钝化屏障中的通孔连接到第一导电互连的第一电极，其使用 第一个面具。 该装置具有用于存储耦合到第一电极的数据的MTJ堆叠。 MTJ堆叠的一部分具有基于第二掩模的横向尺寸。 由第二掩模限定的部分在接触通孔之上。 第二电极耦合到MTJ堆叠并且还具有由第二掩模限定的横向尺寸。 第一电极和MTJ堆叠的一部分由第三掩模限定。 第二导电互连件耦合到第二电极和至少一个其它控制装置。

    INTEGRATING THROUGH SUBSTRATE VIAS INTO MIDDLE-OF-LINE LAYERS OF INTEGRATED CIRCUITS
    36.
    发明申请
    INTEGRATING THROUGH SUBSTRATE VIAS INTO MIDDLE-OF-LINE LAYERS OF INTEGRATED CIRCUITS 有权
    将基板VIAS集成到集成电路的中间层

    公开(公告)号：US20130181330A1

    公开(公告)日：2013-07-18

    申请号：US13724038

    申请日：2012-12-21

    Applicant: QUALCOMM Incorporated

    Inventor： Vidhya Ramachandran ,  Shiqun Gu

    IPC: H01L21/768 ,  H01L23/522

    CPC classification number: H01L21/76804 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor wafer has an integrated, through substrate, via (TSV). The semiconductor wafer includes a substrate. A dielectric layer may be formed on a first side of the substrate. A through substrate via may extend through the dielectric layer and the substrate. The through substrate via may include a conductive material and an isolation layer. The isolation layer may at least partially surround the conductive material. The isolation layer may have a tapered portion.

    Abstract translation: 半导体晶片具有集成的贯穿衬底通孔（TSV）。 半导体晶片包括基板。 电介质层可以形成在衬底的第一侧上。 穿通基板通孔可以延伸通过介电层和基板。 贯通基板通孔可以包括导电材料和隔离层。 隔离层可以至少部分地围绕导电材料。 隔离层可以具有锥形部分。

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