公开(公告)号：US20220085020A1

公开(公告)日：2022-03-17

申请号：US17424621

申请日：2019-11-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei NAGATSUKA ,  Tatsuya ONUKI ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786

Abstract: A novel memory device is provided. Over a driver circuit layer, N memory layers (N is a natural number greater than or equal to 2) including a plurality of memory cells provided in a matrix are stacked. The memory cell includes two transistors and one capacitor. An oxide semiconductor is used as a semiconductor included in the transistor. The memory cell is electrically connected to a write word line, a selection line, a capacitor line, a write bit line, and a read bit line. The write bit line and the read bit line extend in the stacking direction, whereby the signal propagation distance from the memory cell to the driver circuit layer is shortened.

公开(公告)号：US20210175235A1

公开(公告)日：2021-06-10

申请号：US17172153

申请日：2021-02-10

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Yuta ENDO ,  Shuhei NAGATSUKA

IPC: H01L27/108 ,  H01L29/786 ,  H01L49/02 ,  H01L29/24 ,  H01L29/08 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66 ,  H01L21/02 ,  H01L21/465 ,  H01L21/027

Abstract: A semiconductor device including a first oxide including a first region and a second region adjacent to each other and a third region and a fourth region with the first region and the second region sandwiched between the third region and the fourth region, a second oxide over the first region, a first insulator over the second oxide, a first conductor over the first insulator, a second insulator over the second oxide and on side surfaces of the first insulator and the first conductor, a third insulator over the second region and on a side surface of the second insulator, a second conductor over the second region with the third insulator positioned between the second region and the second conductor and on the side surface of the second insulator with the third insulator positioned between the side surface of the second insulator and the second conductor, and a fourth insulator covering the first oxide, the second oxide, the first insulator, the first conductor, the second insulator, the third insulator, and the second conductor and in contact with the third region and the fourth region.

公开(公告)号：US20200343251A1

公开(公告)日：2020-10-29

申请号：US16810902

申请日：2020-03-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Tamae MORIWAKA ,  Yuta ENDO

IPC: H01L27/115 ,  H01L29/786 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/06 ,  G11C7/16 ,  G11C8/14 ,  G11C11/403 ,  G11C11/408 ,  G11C11/24 ,  H01L29/24

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

公开(公告)号：US20200342928A1

公开(公告)日：2020-10-29

申请号：US16962309

申请日：2020-01-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Hitoshi KUNITAKE

IPC: G11C11/408 ,  H01L27/108

Abstract: A novel storage device and a novel semiconductor device are provided.In the storage device, a cell array including a plurality of memory cells is stacked above a control circuit, and the cell array operates separately in a plurality of blocks. Furthermore, a plurality of electrodes are included between the control circuit and the cell array. The electrode is provided for a corresponding block to overlap with the block, and a potential of the electrode can be changed for each block. The electrode has a function of aback gate of a transistor included in the memory cell, and a potential of the electrode is changed for each block, whereby the electrical characteristics of the transistor included in the memory cell can be changed. Moreover, the electrode can reduce noise caused in the control circuit.

公开(公告)号：US20200211628A1

公开(公告)日：2020-07-02

申请号：US16796140

申请日：2020-02-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Shuhei NAGATSUKA

IPC: G11C11/4094 ,  G11C11/4099 ,  G11C7/10 ,  G11C11/405 ,  H01L27/108 ,  G11C11/401 ,  G11C16/04 ,  G11C16/08 ,  G11C16/28

Abstract: A data reading error is reduced. A memory cell array in a storage device includes a write word line, a read word line, a write bit line, a read bit line, a source line, and a gain cell. For example, a read transistor in the gain cell can include a metal oxide in a channel formation region. A cancel circuit is electrically connected to the read bit line. The cancel circuit has a function of supplying, to the read bit line, current for canceling leakage current supplied to the read bit line from the gain cell in a non-selected state. In read operation, a potential change of the read bit line due to leakage current is compensated for by the current from the cancel circuit, so that a data reading error is reduced.

公开(公告)号：US20170084754A1

公开(公告)日：2017-03-23

申请号：US15262660

申请日：2016-09-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka SHIONOIRI ,  Shuhei NAGATSUKA ,  Hideki UOCHI

IPC: H01L29/786 ,  H01L21/78 ,  H01L21/48 ,  H01L23/31 ,  H01L23/544 ,  H01L21/66 ,  H01L23/495 ,  H01L27/12 ,  H01L21/56

CPC classification number: H01L29/78648 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/565 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49555 ,  H01L23/544 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3262 ,  H01L29/7869 ,  H01L2223/54486 ,  H03K19/00346 ,  H05B33/0815 ,  H05B33/089

Abstract: In a logic circuit including transistors with the same conductivity, a reduction in output voltage is prevented with use of at least three transistors and a capacitor. With use of an oxide semiconductor in a semiconductor layer of the transistor, a logic circuit with high output voltage and high withstand voltage is achieved. With use of the logic circuit, a semiconductor device with high output voltage and high withstand voltage is achieved.

公开(公告)号：US20160293276A1

公开(公告)日：2016-10-06

申请号：US15082431

申请日：2016-03-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Kazuaki OHSHIMA

IPC: G11C29/50 ,  G11C11/22

CPC classification number: G11C29/50004 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/401 ,  G11C11/4096 ,  G11C29/50016 ,  H01L27/108

Abstract: The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.

Abstract translation: 半导体器件包括位线，晶体管，保持节点和电容器。 晶体管具有对保留节点进行充电或放电的功能。 电容器具有保持保持节点的电位的功能。 大于写入电压和阈值电压之和的电压被施加到晶体管的栅极。 当晶体管导通时，第一电位以浮置状态的基准电位提供给位线。 小于写入电压和阈值电压之和的电压被施加到晶体管的栅极。 当晶体管导通时，第二电位以浮置状态的基准电位提供给位线。 利用第一和第二电位，晶体管的阈值电压被计算而不受寄生电容和电容器的存储电容的变化的影响。

公开(公告)号：US20160293232A1

公开(公告)日：2016-10-06

申请号：US15083776

申请日：2016-03-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Shuhei NAGATSUKA

IPC: G11C7/12 ,  H01L27/12 ,  G11C7/06 ,  H01L29/786 ,  G11C5/06 ,  H01L27/105 ,  H01L27/092

CPC classification number: G11C7/065 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C7/06 ,  G11C7/12 ,  G11C7/18 ,  G11C8/14 ,  G11C8/16 ,  G11C11/403 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/1108 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/7869 ,  H01L29/78696

Abstract: A column driver includes an amplifier circuit for amplifying data of a read bit line and a latch circuit for retaining the amplified data. The latch circuit includes a pair of nodes Q and QB for retaining complementary data. Data is read from a memory cell in each write target row to a read bit line, and amplified by the amplifier circuit. The amplified data is written to the node Q (or QB) of the latch circuit. In a write target column, write data is input to the latch circuit through the node Q (or QB) to update data of the latch circuit. Then, in each column, data of the latch circuit is written to a write bit line, and the data of the write bit line is written to the memory cell.

Abstract translation: 列驱动器包括用于放大读位线的数据的放大器电路和用于保持放大数据的锁存电路。 锁存电路包括用于保留补充数据的一对节点Q和QB。 数据从每个写目标行中的存储单元读取到读位线，并由放大器电路放大。 放大的数据被写入到锁存电路的节点Q（或QB）。 在写目标列中，通过节点Q（或QB）将写入数据输入到锁存电路，以更新锁存电路的数据。 然后，在各列中，将锁存电路的数据写入写入位线，写入位线的数据被写入存储单元。

公开(公告)号：US20160173097A1

公开(公告)日：2016-06-16

申请号：US14967592

申请日：2015-12-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki INOUE ,  Takanori MATSUZAKI ,  Shuhei NAGATSUKA ,  Takahiko ISHIZU ,  Tatsuya ONUKI

IPC: H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018521 ,  G11C5/147 ,  G11C7/04 ,  G11C7/14 ,  G11C8/08 ,  G11C11/403 ,  G11C11/4085 ,  G11C11/412 ,  G11C11/418 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/1156 ,  H03K3/356182 ,  H03K19/0016

Abstract: To provide a semiconductor device that inhibits unexpected output of a high-level signal immediately after the rise of a power supply voltage. The semiconductor device includes a first buffer circuit, a level shifter circuit, and a second buffer circuit. A first potential is supplied to the first buffer circuit, and a second potential is supplied to the level shifter circuit and the second buffer circuit; consequently, the semiconductor device returns to a normal state. When the semiconductor device returns to a normal state, the second potential is supplied, so that the potential of a node in the level shifter circuit increases. To utilize the increase in the second potential or suppress malfunction due to the increase in the potential, capacitors are provided in the level shifter circuit. This inhibits unexpected operation of a transistor in the level shifter circuit.

Abstract translation: 提供在电源电压上升之后立即抑制高电平信号的意外输出的半导体器件。 半导体器件包括第一缓冲电路，电平移位器电路和第二缓冲电路。 第一电位被提供给第一缓冲电路，第二电位被提供给电平移位器电路和第二缓冲电路; 因此，半导体器件返回到正常状态。 当半导体器件返回到正常状态时，提供第二电位，使得电平移位器电路中的节点的电位增加。 为了利用第二电位的增加或由于电位的增加而抑制故障，在电平移位电路中提供电容器。 这抑制了电平移位器电路中的晶体管的意外的操作。

公开(公告)号：US20160027784A1

公开(公告)日：2016-01-28

申请号：US14873278

申请日：2015-10-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO ,  Shuhei NAGATSUKA ,  Takanori MATSUZAKI ,  Hiroki INOUE

IPC: H01L27/108

CPC classification number: H01L29/7869 ,  G11C16/0425 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/1225 ,  H01L28/40 ,  H01L29/78693 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.