公开(公告)号：US20180151231A1

公开(公告)日：2018-05-31

申请号：US15607636

申请日：2017-05-29

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Francesca Grande ,  Francesco La Rosa ,  Gianbattista Lo Giudice ,  Giovanni Matranga

IPC: G11C16/16 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/26 ,  G11C16/3445

Abstract: A method can be used for reducing a memory operation time in a non-volatile memory device having a memory array with a number of memory cells. The method includes performing a first execution of the memory operation on a set of memory cells by applying a first biasing configuration, storing information associated to the first biasing configuration, and performing a second execution, subsequent to the first execution, of the memory operation on the same set of memory cells by applying a second biasing configuration that is determined according to the stored information associated to the first biasing configuration.

公开(公告)号：US09941369B2

公开(公告)日：2018-04-10

申请号：US15195784

申请日：2016-06-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Julien Delalleau ,  Arnaud Regnier

IPC: H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11521 ,  G11C16/14 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11524 ,  H01L29/78 ,  G11C16/04 ,  H01L21/306

CPC classification number: H01L29/42328 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

公开(公告)号：US20170345836A1

公开(公告)日：2017-11-30

申请号：US15364603

申请日：2016-11-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L27/11531 ,  H01L29/788 ,  H01L29/66 ,  H01L27/11526 ,  H01L27/11521 ,  H01L21/28 ,  H01L21/266 ,  H01L21/265 ,  H01L29/861 ,  G11C16/04

CPC classification number: H01L27/11531 ,  G11C16/045 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28273 ,  H01L27/0629 ,  H01L27/0814 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/1203 ,  H01L29/16 ,  H01L29/36 ,  H01L29/66136 ,  H01L29/66356 ,  H01L29/66825 ,  H01L29/7391 ,  H01L29/7394 ,  H01L29/788 ,  H01L29/861

Abstract: A method can be used to make a semiconductor device. A number of projecting regions are formed over a first semiconductor layer that has a first conductivity type. The first semiconductor layer is located on an insulating layer that overlies a semiconductor substrate. The projecting regions are spaced apart from each other. Using the projecting regions as an implantation mask, dopants having a second conductivity type are implanted into the first semiconductor layer, so as to form a sequence of PN junctions forming diodes in the first semiconductor layer. The diodes vertically extend from an upper surface of the first semiconductor layer to the insulating layer.

公开(公告)号：US20170301378A1

公开(公告)日：2017-10-19

申请号：US15363270

申请日：2016-11-29

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics S.r.l.

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: G11C7/06 ,  G11C8/10 ,  G11C5/14

CPC classification number: G11C7/065 ,  G11C5/14 ,  G11C7/08 ,  G11C8/10

Abstract: A read-amplifier circuit includes a core with a first input and a second input that are intended to receive in a measurement phase a differential signal arising from a first bit line and from a second bit line of the memory device. The circuit also includes a memory element with two inverters coupled in a crossed manner. The first and second inputs are respectively connected to two of the power supply nodes of the inverters via two transfer capacitors. A first controllable circuit is configured to temporarily render the memory element floating during an initial phase preceding the measurement phase and during the measurement phase.

公开(公告)号：US09792962B1

公开(公告)日：2017-10-17

申请号：US15363270

申请日：2016-11-29

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics S.r.l.

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: G11C7/00 ,  G11C7/06 ,  G11C5/14 ,  G11C8/10

CPC classification number: G11C7/065 ,  G11C5/14 ,  G11C7/08 ,  G11C8/10

Abstract: A read-amplifier circuit includes a core with a first input and a second input that are intended to receive in a measurement phase a differential signal arising from a first bit line and from a second bit line of the memory device. The circuit also includes a memory element with two inverters coupled in a crossed manner. The first and second inputs are respectively connected to two of the power supply nodes of the inverters via two transfer capacitors. A first controllable circuit is configured to temporarily render the memory element floating during an initial phase preceding the measurement phase and during the measurement phase.

公开(公告)号：US20170278577A1

公开(公告)日：2017-09-28

申请号：US15365433

申请日：2016-11-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C16/34 ,  G11C16/26 ,  H01L29/788 ,  G11C16/08 ,  H01L27/115 ,  H01L29/792 ,  G11C16/04 ,  G11C16/10

CPC classification number: H01L29/7889 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3427 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/788 ,  H01L29/792

Abstract: The non-volatile memory device comprises memory cells each comprising a selectable state transistor having a floating gate and a control gate. The state transistor is of the depletion-mode type and is advantageously configured so as to have a threshold voltage that is preferably negative when the memory cell is in a virgin state. When the memory cell is read, a read voltage of zero may then be applied to the control gate and also to the control gates of the state transistors of all the memory cells of the memory device.

公开(公告)号：US20170163291A1

公开(公告)日：2017-06-08

申请号：US15140997

申请日：2016-04-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: H03M13/29 ,  G11C29/52 ,  G06F11/10

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/4401 ,  G11C29/70 ,  G11C29/72 ,  G11C29/76 ,  G11C29/82 ,  G11C2029/0409 ,  H03M13/2906

Abstract: A method can be used for managing the operation of a non-volatile memory equipped with a system for correction of a single error and for detection of a double error. In the case of the detection of a defective bit line of the memory plane, a redundant bit line is assigned and the values of the bits of the memory cells of the defective line are copied into the memory cells of the redundant line and are inverted in the case of the detection of double errors by the system, or corrected by the system in the presence of single errors.

公开(公告)号：US20170011804A1

公开(公告)日：2017-01-12

申请号：US15276462

申请日：2016-09-26

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C16/26 ,  H01L27/115 ,  G11C16/08 ,  H01L21/28 ,  G11C16/04 ,  G11C16/14

CPC classification number: G11C16/26 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/08 ,  G11C16/14 ,  H01L21/0276 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11524

Abstract: The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer.

Abstract translation: 本公开涉及一种半导体衬底上的非易失性存储单元，包括：第一晶体管，包括控制栅极，浮置栅极和漏极区域;第二晶体管，包括控制栅极，浮置栅极和漏极区域， 其中第一和第二晶体管的浮置栅极电耦合，并且第二晶体管包括电耦合到其漏极区域并且通过隧道电介质层与其浮动栅极相对延伸的导电区域。

公开(公告)号：US09543018B2

公开(公告)日：2017-01-10

申请号：US14964196

申请日：2015-12-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: G11C8/10 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C8/12 ,  G11C8/08

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26

Abstract: The present disclosure relates to a memory including a memory array with at least two rows of memory cells, a first driver coupled to a control line of the first row of memory cells, and a second driver coupled to a control line of the second row of memory cells. The first driver is made in a first well, the second driver is made in a second well electrically insulated from the first well, and the two rows of memory cells are produced in a memory array well electrically insulated from the first and second wells.

Abstract translation: 本公开涉及包括具有至少两行存储器单元的存储器阵列的存储器，耦合到第一行存储器单元的控制线的第一驱动器和耦合到第二行存储器单元的控制线的第二驱动器 记忆细胞 第一驱动器在第一阱中制造，第二驱动器在与第一阱电绝缘的第二阱中制造，并且两行存储器单元在与第一阱和第二阱良好地电绝缘的存储器阵列中产生。

公开(公告)号：US09506964B2

公开(公告)日：2016-11-29

申请号：US13669741

申请日：2012-11-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: G01R27/26 ,  G06F3/041 ,  G06F3/044

CPC classification number: G01R27/2605 ,  G06F3/0416 ,  G06F3/044

Abstract: The disclosure comprises: linking a first terminal of the capacitance to the mid-point of a first voltage divider bridge, applying a first voltage to a second terminal of the capacitance, maintaining a voltage of a mid-point of the first divider bridge near a reference voltage, and discharging a mid-point of a second divider bridge with a constant current. When a voltage of the mid-point of the second bridge reaches a first voltage threshold, applying a second voltage to the second terminal of the capacitance, and measuring the time for the voltage to reach a second threshold.

Abstract translation: 本公开包括：将电容的第一端子连接到第一分压器桥的中点，将第一电压施加到电容的第二端子，将第一分压器桥的中点的电压保持在 参考电压，并以恒定电流放电第二分频器桥的中点。 当第二桥的中点的电压达到第一电压阈值时，向电容的第二端施加第二电压，并测量电压达到第二阈值的时间。