公开(公告)号：US09673140B2

公开(公告)日：2017-06-06

申请号：US14620328

申请日：2015-02-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chia-Cheng Chen ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Yu-Cheng Pai ,  Don-Son Jiang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/16

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/15156 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/19103 ,  H01L2924/37001 ,  H01L2924/014

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a laminate on the carrier, wherein the laminate has a built-up portion and a release portion smaller in size than the built-up portion, the release portion covering the bonding pads and the built-up portion being laminated on the release portion and the carrier; forming a plurality of conductive posts in the built-up portion; and removing the release portion and the built-up portion on the release portion such that a cavity is formed in the laminate to expose the bonding pads, the conductive posts being positioned around a periphery of the cavity. Therefore, the present invention has simplified processes.

公开(公告)号：US09640503B2

公开(公告)日：2017-05-02

申请号：US14837245

申请日：2015-08-27

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ming-Chen Sun ,  Chun-Hsien Lin ,  Tzu-Chieh Shen ,  Shih-Chao Chiu ,  Yu-Cheng Pai

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  H05K3/20 ,  H05K3/42

CPC classification number: H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8182 ,  H01L2924/15313 ,  H05K1/111 ,  H05K3/20 ,  H05K3/205 ,  H05K3/428 ,  H05K2201/0376 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.

公开(公告)号：US09510463B2

公开(公告)日：2016-11-29

申请号：US14583317

申请日：2014-12-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Chun-Hsien Lin ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H05K3/40 ,  H05K3/46 ,  H05K3/20

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H05K3/20 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/10674

Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.

Abstract translation: 提供了一种无芯封装基板，其包括：具有相对的第一和第二表面的电介质层; 所述第一电路层嵌入在所述电介质层中并且从所述电介质层的所述第一表面露出，其中所述第一电路层具有多个第一导电焊盘; 分别形成在第一导电焊盘上的多个突起元件，其中每个突出元件具有被外部导电元件封装的接触表面; 形成在电介质层的第二表面上的第二电路层; 以及形成在电介质层中的多个导电通孔，用于电连接第一电路层和第二电路层。 本发明由于突出元件和导电元件之间的大的接触面积而增强了第一导电焊盘和导电元件之间的接合。

公开(公告)号：US20160071780A1

公开(公告)日：2016-03-10

申请号：US14603844

申请日：2015-01-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Ming-Chen Sun ,  Yu-Cheng Pai ,  Tzu-Chieh Shen

IPC: H01L23/31 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/92242 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/014

Abstract: A method of fabricating a semiconductor package is provided, including providing a carrier provided having a circuit layer and a blocking member, forming on the carrier an encapsulating layer having a first surface and a second surface opposing the first surface and encapsulating the circuit layer and the blocking member, with the first surface coupled with the carrier, and removing the carrier and the blocking member to form in the encapsulating layer via the first surface thereof an opening for an electronic component to be received therein. Before the electronic component is disposed in the opening, the circuit layer and the electronic component can be tested in advance, in order to retire the defectives. Therefore, as a defective electronic component is prevented from being disposed in the opening, no defective semiconductor package will be fabricated.

Abstract translation: 提供一种制造半导体封装的方法，包括提供具有电路层和阻挡构件的载体，在载体上形成具有第一表面和与第一表面相对的第二表面的封装层，并封装电路层和 阻挡构件，其中第一表面与载体联接，并且移除载体和阻挡构件，以在封装层中经由其第一表面形成用于待接纳在其中的电子部件的开口。 在将电子部件设置在开口内之前，可以预先测试电路层和电子部件，以便退出缺陷。 因此，由于防止有缺陷的电子元件被布置在开口中，所以不会制造有缺陷的半导体封装。

公开(公告)号：US20150287671A1

公开(公告)日：2015-10-08

申请号：US14620328

申请日：2015-02-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chia-Cheng Chen ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Yu-Cheng Pai ,  Don-Son Jiang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/492

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/15156 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/19103 ,  H01L2924/37001 ,  H01L2924/014

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a laminate on the carrier, wherein the laminate has a built-up portion and a release portion smaller in size than the built-up portion, the release portion covering the bonding pads and the built-up portion being laminated on the release portion and the carrier; forming a plurality of conductive posts in the built-up portion; and removing the release portion and the built-up portion on the release portion such that a cavity is formed in the laminate to expose the bonding pads, the conductive posts being positioned around a periphery of the cavity. Therefore, the present invention has simplified processes.

Abstract translation: 提供了一种制造封装结构的方法，其包括以下步骤：提供具有多个焊盘的载体; 在载体上层叠层压体，其中层压体具有积累部分和尺寸小于组合部分的剥离部分，覆盖接合焊盘的释放部分和积层部分层压在释放部分上， 承运人 在所述积层部中形成多个导电柱; 以及在所述释放部分上移除所述释放部分和所述积累部分，使得在所述层压体中形成空腔以露出所述接合焊盘，所述导电柱位于所述空腔的周边周围。 因此，本发明具有简化的处理。

公开(公告)号：US20150028485A1

公开(公告)日：2015-01-29

申请号：US13950638

申请日：2013-07-25

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Liang-Yi Hung ,  Shih-Chao Chih ,  Yu-Cheng Pai ,  Wei-Chung Hsiao

IPC: H01L23/48

CPC classification number: H01L23/498 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81447 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A substrate structure is provided. The substrate structure includes a substrate body; a metal layer formed on a surface of the substrate body; an insulating layer formed on the surface of the substrate body and having at least an opening for exposing the metal layer; and at least a die attach area defined on the surface of the substrate body corresponding in position to the opening for a semiconductor chip to be disposed thereon. The die attach area covers the entire opening or the metal layer is formed within the die attach area, thereby effectively preventing package delamination and improving the product yield.

Abstract translation: 提供了基板结构。 衬底结构包括衬底本体; 形成在所述基板主体的表面上的金属层; 绝缘层，其形成在所述基板主体的表面上，并且至少具有用于使所述金属层露出的开口; 以及至少一个限定在基板主体的表面上的芯片附着区域，其对应于要布置在其上的半导体芯片的开口的位置。 芯片附着区域覆盖整个开口，或者在芯片附着区域内形成金属层，从而有效地防止封装分层并提高产品产量。

公开(公告)号：US10096491B2

公开(公告)日：2018-10-09

申请号：US14755372

申请日：2015-06-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Chun-Hsien Lin ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Liang-Yi Hung

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

Abstract: A method of fabricating a packaging substrate is provided, including: providing a carrier having two carrying portions, each of the carrying portions having a first side and a second side opposite to the first side and the carrying portions are bonded through the second sides thereof; forming a circuit layer on the first side of each of the carrying portions; and separating the two carrying portions from each other to form two packaging substrates. The carrying portions facilitate the thinning of the circuit layers and provide sufficient strength for the packaging substrates to undergo subsequent packaging processes. The carrying portions can be removed after the packaging processes to reduce the thickness of packages and thereby meet the miniaturization requirement.

公开(公告)号：US10002825B2

公开(公告)日：2018-06-19

申请号：US15625083

申请日：2017-06-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H05K1/18 ,  H01L23/538 ,  H05K3/00 ,  H01L21/683 ,  H05K3/32 ,  H05K3/10 ,  H01L23/00 ,  H05K1/02 ,  H05K3/46 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/189 ,  H05K3/0026 ,  H05K3/007 ,  H05K3/108 ,  H05K3/32 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665

Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.

公开(公告)号：US20170352615A1

公开(公告)日：2017-12-07

申请号：US15625083

申请日：2017-06-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H01L23/538 ,  H05K3/32 ,  H05K3/00 ,  H05K1/18 ,  H01L21/683 ,  H05K3/46 ,  H01L23/00 ,  H01L23/31 ,  H05K1/02 ,  H05K3/10

CPC classification number: H01L23/49838 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/189 ,  H05K3/0026 ,  H05K3/007 ,  H05K3/108 ,  H05K3/32 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665

Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.

公开(公告)号：US20170301658A1

公开(公告)日：2017-10-19

申请号：US15636217

申请日：2017-06-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Chun-Hsien Lin ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L25/10 ,  H01L21/48 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1533 ,  H05K1/111 ,  H05K3/4697 ,  H05K2201/10674

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a dielectric layer on the carrier; forming a plurality of conductive posts in the dielectric layer; and forming a cavity in the dielectric layer to expose the bonding pads, wherein the conductive posts are positioned around a periphery of the cavity, thereby simplifying the fabrication process.