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    DYNAMIC MANAGEMENT OF WRITE-MISS BUFFER TO REDUCE WRITE-MISS TRAFFIC
    34.
    发明申请
    DYNAMIC MANAGEMENT OF WRITE-MISS BUFFER TO REDUCE WRITE-MISS TRAFFIC 审中-公开
    写作错误缓冲区的动态管理减少了写错误的交通

    公开(公告)号：US20150006820A1

    公开(公告)日：2015-01-01

    申请号：US13973306

    申请日：2013-08-22

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Naveen Bhoria ,  Joseph Raymond Michael Zbiciak ,  Raguram Damodaran ,  Abhijeet Ashok Chachad

    IPC: G06F12/08

    CPC classification number: G06F12/0811

    Abstract: Traffic output from a cache write-miss buffer is controlled by determining whether a predetermined condition is satisfied, and outputting an oldest entry from the buffer only in response to a determination that the predetermined condition is satisfied. Posting of a new entry to the buffer is insufficient to satisfy the predetermined condition.

    Abstract translation: 通过确定是否满足预定条件来控制来自高速缓存写入 - 未命中缓冲器的流量输出，并且仅响应于满足预定条件的确定从缓冲器输出最旧的条目。 向缓冲器发送新条目不足以满足预定条件。

    Memory pipeline control in a hierarchical memory system
    35.
    发明授权
    Memory pipeline control in a hierarchical memory system 有权

    公开(公告)号：US12197332B2

    公开(公告)日：2025-01-14

    申请号：US18584181

    申请日：2024-02-22

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  Timothy Anderson ,  Kai Chirca ,  David Matthew Thompson

    IPC: G06F12/00 ,  G06F1/14 ,  G06F9/38 ,  G06F9/54 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/0888

    Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

    PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE
    40.
    发明公开
    PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE 审中-公开

    公开(公告)号：US20240256464A1

    公开(公告)日：2024-08-01

    申请号：US18630098

    申请日：2024-04-09

    Applicant: Texas Instruments Incorporated

    Inventor： Bipin Prasad Heremagalur Ramaprasad ,  David Matthew Thompson ,  Abhijeet Ashok Chachad ,  Hung Ong

    IPC: G06F12/1045 ,  G06F15/78

    CPC classification number: G06F12/1045 ,  G06F15/7807 ,  G06F2212/301 ,  G06F2212/50

    Abstract: A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.

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